Verilog HDL
HDLs provide ways to represent the digital circuits in the textual form. Verilog HDL is a HARDWARE DESCRIPTION LANGUAGE to model the digital circuits, the source code is written in a text file with the extension [*. v].
Any Verilog HDL source code is created with the combination of IDENTIFIERS and KEYWORDS which are also called as SYNTAX/SEMANTICS. These are globally called lexical tokens. Combination of more than one lexical token originate LEXICAL CONVENTIONS.
1. Introduction & Overview of Verilog HDL
5. Variables & Data Types and Vector Arrays
5.2.4. scalar vs vector vs arrays
8.1. $display vs $monitor vs $strobe vs $write
8.2. $random : Random Number Generation
9. Design and Testbench Creation
9.1. Module Structure & Elements
9.4. Design Module Fundamentals
9.5. Testbench Creation Techniques
10. Verilog Operators and Operands
11. Gate-Level Modeling/Designing of Digital Circuits
11.1. Pre-defined Gate Primitives
12. Switch-Level Modeling/Designing
12.1. Understanding MOS Behaviour
12.2.4. Resistive MOS Switches
12.3. Drive Strength and Resolution
13. Data-Flow Modeling/Designing
14. Behavioural Modeling/Designing
14.1. Behavioural Blocks (initial & always)
14.2. Sequential and Parallel Blocks
14.3. Blocking and Non-Blocking Assignments
14.4. Timing Controls
14.4.1. Delay Based Timing Controls
14.4.2. Event Based Timing Controls
14.4.3. Level Sensitive Timing Controls
14.4.4. Advanced Timing Techniques
14.5. Multiway Branching
14.5.1. If/Else Statements
14.5.2. Case Statements
14.5.3. Advanced Techniques
14.6. Loops
14.6.1. For Loop
14.6.2. While Loop
14.6.3. Repeat Loop
14.6.4. Forever Loop
14.6.5. Advanced Techniques
14.7. Generate Block
14.7.1. Generate for
14.7.2. Generate if
14.7.3. Generate case
14.7.4. Advanced Generate Techniques
15.1. Function
15.2. Task
15.3. Static and Automatic Behaviour
15.4. Re-entrant task and functions
15.5. Advanced Techniques
16. User Defined Primitives (UDPs)
16.1. Combinational UDPs
16.2. Sequential UDPs
16.3. Advanced Techniques
17. Delay Modeling
17.1. Distributed Delay
17.2. Lumped Delay
17.3. Pin-to-Pin Delay
17.4. Specify Block
18. Timing Checks
19. Timing Regions
VERILOG LABS
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Designing of Logic Gates
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Designing of Combinational Circuits
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Designing of Multiple Shift Registers
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Designing of Pattern Detector FSM