9.1 Module Structure & Elements
Understanding the Verilog Module
A module is the basic building block in Verilog and SystemVerilog. It encapsulates functionality and can represent anything from a simple gate to a complete processor. Understanding module structure is crucial for writing clean, maintainable, and synthesizable code.
​
Basic Module Anatomy
​
Every Verilog module consists of several key elements:
Verilog
Module Elements Breakdown
1. Port Declarations
Ports define the interface of your module:
- Input ports: Data flows into the module
- Output ports: Data flows out of the module
- Inout ports: Bidirectional data flow (used for tristate buses)
Port types:
Verilog
2. Parameter Declarations
Parameters make your design configurable and reusable:
Verilog
3. Internal Signal Declarations
Internal signals connect different parts of your design:
Verilog
4. Continuous Assignments
Used for combinational logic:
Verilog
5. Procedural Blocks
Always blocks for sequential and combinational logic:
Verilog
6. Tasks and Functions
For code reusability:
Verilog
Best Practices for Module Structure
1. Clear Port Naming: Use descriptive names (e.g., `addr_valid` instead of `av`)
​
2. Consistent Coding Style: Follow a standard (IEEE, company-specific)
​
3. Proper Comments: Document complex logic and design decisions
​
4. Separation of Concerns: Keep combinational and sequential logic separate
​
5. Reset Strategy: Always include proper reset logic
​
6. Avoid Mixed Assignments: Don't mix blocking and non-blocking assignments