5.2.1 The `integer` Data Type
Overview
The integer data type is a signed 32-bit register type designed for arithmetic operations and loop counters. It provides a convenient way to perform mathematical calculations in Verilog.
Syntax and Declaration
Verilog
integer variable_name;
integer variable_name1, variable_name2, variable_name3;
Characteristics
-
Fixed width: Always 32 bits
-
Signed: Can represent positive and negative values
-
Range: -2,147,483,648 to +2,147,483,647
​
-
Two's complement: Uses two's complement representation for negative numbers
Examples
Verilog
module integer_examples;
integer count;
integer result, operand1, operand2;
initial begin
count = 0;
operand1 = 25;
operand2 = -10;
result = operand1 + operand2; // result = 15
// Loop counter usage
for (count = 0; count < 10; count = count + 1) begin
$display("Count: %d", count);
end
end
endmodule
Common Use Cases
​
-
Loop counters in `for` loops
​
-
Temporary variables in calculations
-
Array indexing
​
-
Mathematical computations
Verilog
// Loop counters
integer i, j, k;
for (i = 0; i < 8; i = i + 1) begin
// Process data
end​
// Mathematical calculations
integer dividend = 100;
integer divisor = 7;
integer quotient = dividend / divisor;
Verilog
// Always initialize variables
reg [7:0] counter = 8'h00;
integer loop_var = 0;
real temperature = 25.0;
Integer Overflow
Verilog
// Problem: Integer overflow
integer large_num = 2147483647;
large_num = large_num + 1; // Overflow!
// Solution: Use wider reg types for large numbers
reg [63:0] large_reg = 64'h7FFFFFFF;