System Verilog
As we know, HDLs provide ways to represent the digital circuits in the textual form. Verilog HDL is a HARDWARE DESCRIPTION LANGUAGE to model the digital circuits, the source code is written in a text file with the extension [*. v]. [Click here for Verilog]
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System Verilog is of both types HARDWARE DESCRIPTION LANGUAGE (HDL) and HARDWARE VERIFICATION LANGUAGE (HVL). It is also called as enhancement of Verilog HDL. The source code is written in a text file with the extension [*. sv].
Any System Verilog source code is created with the combination of IDENTIFIERS and KEYWORDS which are also called as SYNTAX/SEMANTICS. All the lexical conventions of Verilog HDL are supported in System Verilog.
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We can say that (Verilog + OOPs = System Verilog). But, its not the complete difference among both the languages. ​
All the concepts in Verilog are enhanced in System Verilog, we have explained each and every concepts of System Verilog in relation with Verilog so that readers can easily imagine the connection between Verilog and System Verilog.
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Below points describes the few more differences between Verilog and SV:
Verification Enhancements
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Objected Oriented Programming (OOPs): concepts are newly added in System Verilog for creating highly scalable and reusable testbench to verify high performance designs.
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Interface: is newly added for resolving connection related issues between complex designs and testbench.
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Randomization: is the key concept for generating random inputs. Constraints are also added for limitation of range in which generated input value lies.
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Coverage: is introduced for capturing the information of the design and testbench while running the simulations.
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Assertions: are added for verification of particular part of design directly without running simulations.
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Packages, Program Block, Inter Process Communication (IPC)- Mailbox and Semaphore: are newly added for making smooth verification process.
Designing Enhancements
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Port Mapping Rules: are added for better connections between design hierarchy.
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Behavioural Blocks: Three procedural blocks are newly added for resolving ambiguity errors as well as design blockage/deadlock issue.
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always_comb: models combinational circuits.​
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always_latch: models latch circuits.
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always_ff: models flip flop circuits.
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Task & Function: are enhanced for introducing better reusability and splitting the larger code into smaller parts.​
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Operator and Loop: are enhanced for reducing the complexity of boolean expression.
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Lexical Conventions: are enhanced for better control over the language.
SystemVerilog Course Index (Detailed)
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1. Introduction to SystemVerilog
1.1. What is SystemVerilog?
1.2. Why SystemVerilog? Evolution from Verilog
1.3. SystemVerilog vs Verilog: Key Differences
1.4. Design vs Verification in SystemVerilog
1.5. Compilation Units, Files, and Libraries
1.6. Tool Flow: Simulation vs Synthesis
1.7. SystemVerilog Standards Overview (IEEE 1800)
1.8. Common Use Cases in Industry​
2. SystemVerilog Basics and Syntax
2.1. Lexical Structure: Tokens, Identifiers, Keywords
2.2. Comments and Compiler Directives
2.3. Modules and Programs
2.4. Ports, Nets, and Variables
2.5. Data Types Overview: 2-state vs 4-state
2.6. Operators: Arithmetic, Logical, Bitwise, Reduction
2.7. Assignments: Blocking vs Non-blocking
2.8. Procedural Blocks: initial, always
2.9. always_comb, always_ff, always_latch
2.10. Statements: if/else, case, loops
2.11. Tasks and Functions Basics
2.12. Packages and Importing
2.13. Compilation and Simulation Basics
3. Data Types and Variables
3.1. 2-state Types: bit, byte, int
3.2. 4-state Types: logic, reg
3.3. Signed vs Unsigned
3.4. Integer Types: shortint, longint, integer
3.5. Real Types: real, shortreal, realtime
3.6. String Data Type
3.7. Enum Types
3.8. Structs: Packed and Unpacked
3.9. Unions: Packed and Unpacked
3.10. Type Casting: static and dynamic
3.11. $cast usage
3.12. Typedef
3.13. User-defined Types and Aliases
4. Arrays and Memory Structures
4.1. Packed Arrays
4.2. Unpacked Arrays
4.3. Multi-dimensional Arrays
4.4. Dynamic Arrays
4.5. Associative Arrays
4.6. Queues
4.7. Array Methods and Iterators
4.8. Array Slicing and Streaming Operators
4.9. Memory Modeling Techniques
4.10. Common Pitfalls and Best Practices
5. Procedural Blocks and Timing
5.1. Procedural Execution Model
5.2. Event Scheduling Regions
5.3. Delay Control: #delay
5.4. Event Control: @, posedge/negedge
5.5. Wait Statements
5.6. Fork-Join Variants: join, join_any, join_none
5.7. Disable Fork and Named Blocks
5.8. Race Conditions and Avoidance
5.9. Clocking and Reset Strategies
6. Tasks, Functions, and DPI
6.1. Task vs Function Differences
6.2. Automatic vs Static Tasks/Functions
6.3. Pass by Value vs Reference
6.4. Input/Output/Inout Arguments
6.5. Default Arguments
6.6. Recursive Functions
6.7. Extern Declarations
6.8. Import/Export DPI Basics
6.9. Calling C Functions from SV
6.10. Practical DPI Examples
7. Interfaces and Modports
7.1. Interface Basics
7.2. Interface Ports and Signals
7.3. Modports
7.4. Clocking Blocks
7.5. Virtual Interfaces
7.6. Connecting Interfaces to DUT
7.7. Best Practices for Interface Usage
7.8. Common Errors and Debugging
8. Object-Oriented Programming in SystemVerilog
8.1. Classes and Objects
8.2. Class Properties and Methods
8.3. Constructors and Destructors
8.4. Inheritance and Method Overriding
8.5. Virtual Methods and Polymorphism
8.6. Abstract Classes and Pure Virtual Methods
8.7. Interface Classes
8.8. Static Class Members
8.9. This, Super Keywords
8.10. Deep Copy vs Shallow Copy
8.11. Cloning and Copy Methods
8.12. Class Randomization
8.13. Common OOP Interview Questions
9. Assertions (SVA)
9.1. Immediate Assertions
9.2. Concurrent Assertions
9.3. Property and Sequence Basics
9.4. Implication Operators (|->, |=>)
9.5. Repetition Operators
9.6. Disable iff
9.7. Clocking Event and Sampling
9.8. Assertions for Protocol Checking
9.9. Cover Properties
9.10. Assertions Debugging Techniques
9.11. Best Practices and Common Pitfalls
10. Constrained Random Verification
10.1. Random Variables and rand/randc
10.2. Constraints Basics
10.3. Constraint Blocks and Inline Constraints
10.4. Constraint Inheritance
10.5. Soft Constraints
10.6. Static Constraints
10.7. Constraint Modes and Disabling
10.8. Randomize with()
10.9. Distribution Constraints
10.10. Solve Before
10.11. Pre/Post Randomize Methods
10.12. Constraint Debugging
10.13. Coverage-driven Randomization
11. Functional Coverage
11.1. Coverage Concepts and Goals
11.2. Covergroups and Coverpoints
11.3. Bins: Default, Illegal, Ignore
11.4. Cross Coverage
11.5. Coverage Options and Weights
11.6. Sampling Events
11.7. Coverage in Classes
11.8. Merging Coverage
11.9. Coverage Reports and Analysis
11.10. Best Practices for Coverage Closure
12. Interprocess Communication and Synchronization
12.1. Events
12.2. Mailboxes
12.3. Semaphores
12.4. Processes and Threads
12.5. Wait Fork
12.6. Process Control and Kill
12.7. Synchronization Patterns
12.8. Common Use Cases in Testbenches
13. Testbench Architecture and Methodologies
13.1. Basic Testbench Components
13.2. Directed vs Random Testing
13.3. Scoreboarding Concepts
13.4. Reference Models
13.5. Monitors and Drivers
13.6. Transaction-Level Modeling (TLM) Basics
13.7. Reusable Testbench Design
13.8. Layered Testbench Approach
13.9. Introduction to UVM
13.10. Common Debugging Strategies
14. SystemVerilog for Synthesis
14.1. Synthesizable Constructs
14.2. always_ff/always_comb Guidelines
14.3. Coding Style for Synthesis
14.4. FSM Coding Techniques
14.5. Resource Sharing and Optimization
14.6. Synthesis Pitfalls
14.7. Linting and Coding Rules
14.8. Best Practices for RTL Designers
15. Advanced SystemVerilog Topics
15.1. Streaming Operators
15.2. Random Stability and Seed Control
15.3. Parameterized Classes
15.4. Generate Constructs
15.5. Macros and Compiler Directives
15.6. Packages and Namespaces
15.7. SystemVerilog Interfaces in Complex Designs
15.8. Performance Optimization in Simulation
15.9. Common Real-world Debug Scenarios