5.1.2 Signal Strengths

• In Verilog, signal strength determines how strongly a signal drives a logic value (0, 1, or Z) on a net. It plays a key role in resolving logic values when multiple drivers are connected to a net (like tri or wire).

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• When multiple drivers assign values to a net (e.g., wire), the resulting logic value is determined by the strongest driver.

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• It's especially important in bus systems, tri-state buffers, and bidirectional lines.

Strength Available in Verilog HDL​

Strength Level                                           Type                                                  Degree

supply0, supply1

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strong0, strong1

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pull0,

pull1

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large0,

large1

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weak0,

weak1

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medium0, medium1

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small0, small1

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highz0, highz1