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14.6.4. Forever Loop
The forever loop creates an infinite loop that continues until explicitly disabled or simulation ends. It is exclusively used in testbenches for continuous operations like clock generation and monitoring.
Syntax and Structure
Verilog
Characteristics
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Executes infinitely (no termination condition)
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MUST contain timing control (#delay or @event)
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Typically used in initial blocks
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Can be stopped with disable statement
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NOT synthesizable (testbench only)
Primary Use: Clock Generation
Verilog
Other Forever Loop Applications
Verilog
Controlling Forever Loops
Using disable Statement
Verilog
Using $finish
Verilog
Critical: Must Have Timing Control
⚠ CRITICAL: Forever loops MUST contain timing control or they create infinite zero-time loops that HANG the simulator!
Verilog
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