18. Introduction to Timing Checks
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Timing checks are system tasks used within specify blocks to verify that timing constraints are met during simulation. They detect violations like setup time violations, hold time violations, and pulse width violations that could cause circuit malfunction in real hardware.
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Why Timing Checks?
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Verify Timing Constraints: Ensure design meets timing requirements
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Detect Violations: Find setup, hold, width violations early
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Prevent Metastability: Catch conditions that cause unstable states
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Library Characterization: Define cell timing requirements
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STA Correlation: Match static timing analysis results
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Where Timing Checks are Used
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Inside specify blocks of modules
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Standard cell libraries
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Memory models (SRAM, Register File)
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Sequential elements (Flip-flops, Latches)
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Interface timing verification
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Timing Check Reporting
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When a timing violation occurs, simulators report:
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Violation type (setup, hold, width, etc.)
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Time of violation
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Actual vs required timing
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Instance path where violation occurred
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Severity level (error, warning)
Complete Timing Checks Overview
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18.1. $setup - Setup Time Check
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The setup time is the minimum time that a data signal must be stable BEFORE the active edge of the clock. This ensures the data is properly captured by the flip-flop.
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Syntax
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$setup(data_event, reference_event, limit);
$setup(data_event, reference_event, limit, notifier);
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Parameters
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Industry-Standard Examples
Verilog
Timing Diagram
SETUP TIME VIOLATION:
tsu (Setup Time)
<------>
DATA: ----X======X------
change
CLK: ________|‾‾‾‾‾‾|___
↑
Clock edge
PASS: Data change > tsu before clock
FAIL: Data change < tsu before clock
18.2. $hold - Hold Time Check
The hold time is the minimum time that a data signal must remain stable AFTER the active edge of the clock. This ensures data is not corrupted during capture.
Syntax
$hold(reference_event, data_event, limit);
$hold(reference_event, data_event, limit, notifier);
Industry-Standard Examples
Verilog
Timing Diagram
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HOLD TIME VIOLATION:
th (Hold Time)
<------>
DATA: ----========X------
change
CLK: ________|‾‾‾‾‾‾|___
↑
Clock edge
PASS: Data change > th after clock
FAIL: Data change < th after clock
18.3. $setuphold - Combined Setup and Hold
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$setuphold combines setup and hold checks in a single statement, which is more efficient and commonly used in standard cell libraries.
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Syntax
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$setuphold(reference_event, data_event, setup_limit, hold_limit);
$setuphold(reference_event, data_event, setup_limit, hold_limit, notifier);
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Industry-Standard Examples
Verilog
18.4. $width - Pulse Width Check
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$width checks that a signal's pulse (high or low) meets the minimum width requirement. This is critical for clock signals and control signals.
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Syntax
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$width(controlled_reference_event, limit);
$width(controlled_reference_event, limit, threshold, notifier);
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Width Types
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Industry-Standard Examples
Verilog
Timing Diagram
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PULSE WIDTH CHECK:
<--- twidth_high --->
CLK: __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
↑ ↑
posedge negedge
<--- twidth_low --->
CLK: ‾‾|__________________|‾‾‾
↑ ↑
negedge posedge