top of page

14.4.3. Level-Sensitive Timing Controls

Level-sensitive timing controls use the wait statement to suspend execution until a boolean condition becomes true. Unlike event controls that trigger on transitions, wait statements continuously monitor a condition.

14.4.3.1 wait Statement

Syntax and Basic Usage

Verilog

Characteristics

Continuously evaluates condition

Proceeds immediately if condition is already true

Waits if condition is false

Level-sensitive (not edge-sensitive)

NOT synthesizable (testbench only)

wait vs @ Comparison

Verilog

14.4.3.2 Detailed Behavioral Differences

Screenshot (750).png

Practical Examples

Verilog

Behavior Scenarios

Verilog

Event based timing control

Advanced timing techniques

bottom of page