4.2 Comments Implementation
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Comments are used to increase the readability of code.
​
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Comments are specifically added in the code for future reference by the designers.
​
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Comments are ignored by the Simulator.
​
​
Verilog HDL has two types of comment which are given below:
4.2.1. Single Line Comment
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// This line is commented.
Verilog
module u_op;
initial begin
$display (“This is VLSI Mentor E - Learning Platform.”);
//$display (“Here, users can learn VLSI Courses.”);
end
endmodule
Output
This is VLSI Mentor E - Learning Platform.
​4.2.2. Multi-Line Comment
​
/* This line is commented.
This line is commented too. */
Verilog
module u_op;
initial begin
$display (“This is VLSI Mentor E - Learning Platform.”);
/*
$display (“Here, users can learn Verilog HDL.”);
$display (“Here, users can learn SystemVerilog.”);
$display (“Here, users can learn UVM.”);
$display (“Here, users can learn C/C++.”);
*/
end
endmodule
Output
This is VLSI Mentor E - Learning Platform.