4.5 String
A string is a sequence of characters enclosed by double quotes (“) and contained on a single line. Strings used as operands in expressions and assignments shall be treated as unsigned integer constants represented by a sequence of 8-bit ASCII values, with one 8-bit ASCII value representing one character.
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4.5.1. String Representation in Verilog
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In Verilog, a string is essentially a sequence of characters stored in a reg array. Each character is represented by its 8-bit
ASCII value. For example:​​
Verilog
reg [8*14-1:0] my_string; // A string of up to 14 characters
Here:
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8 represents the number of bits per character (ASCII).
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14 is the maximum number of characters in the string.
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The total width of the reg is 8 * 14 = 112 bits.​​
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4.5.2. Assigning Strings​
You can assign a string to a reg array using double quotes ("):
Verilog
reg [8*14-1:0] my_string;
initial begin
my_string = "Hello, World!"; // Assign a string
end
If the string is shorter than the declared length, the remaining bits are padded with zeros.If the string is longer than the declared length, it will be truncated.