11.1. Predefined Gate Primitives in Verilog: Complete Reference
Introduction
Verilog provides a comprehensive set of built-in gate primitives that represent fundamental logic gates and switches. These primitives are the building blocks of gate-level modeling and are essential for understanding how digital circuits are implemented in hardware.
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Syntax:
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primitive_type [#delay] instance_name (output, input1, input2, ...);
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Example:
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and and_gate1 (y, a, b); // 2-input AND gate
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Characteristics:
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- Pre-built: No need to define their behavior
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- Instantiated: Used like modules with instance names
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- Hardware-mapped: Directly correspond to physical gates
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- Simulation models: Include timing and strength information
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What You'll Learn:
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- Complete reference of all Verilog gate primitives
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- Syntax and usage of each primitive type
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- Practical applications and examples
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- Strength modeling and resolution
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- Interview-focused concepts
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- Industry best practices
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Understanding gate primitives is crucial for:
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- Writing gate-level netlists
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- Understanding synthesizer output
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- Post-synthesis simulation
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- Low-level circuit design
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11.1.1. Basic Logic Gates
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1. AND Gate
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Implements logical AND operation.
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Truth Table:
Syntax:
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and instance_name (output, input1, input2, ... inputN);
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Examples:
Verilog
Applications:
- Enable signals
- Masking operations
- Control logic
2. OR Gate
Implements logical OR operation.
Truth Table:
Syntax:
or instance_name (output, input1, input2, ... inputN);
Examples:
Verilog
Applications:
- Combining signals
- Priority logic
- Status flags
3. NOT Gate (Inverter)
Implements logical NOT operation (inversion).
Truth Table:
Syntax:
not instance_name (output, input);
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Examples:
Verilog
Applications:
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- Signal inversion
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- Complement generation
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- Logic negation
4. NAND Gate
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Implements logical NAND operation (NOT-AND).
Truth Table:
Syntax:
nand instance_name (output, input1, input2, ... inputN);
Examples:
Verilog
Special Properties:
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- Universal gate (can implement any logic function)
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- Commonly used in CMOS design
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- Lower power than AND-NOT combination
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NAND as Universal Gate:
Verilog
5. NOR Gate
Implements logical NOR operation (NOT-OR).
Truth Table:
Syntax:
nor instance_name (output, input1, input2, ... inputN);
Examples:
Verilog
Special Properties:
- Universal gate (can implement any logic function)
- Used in SR latches
- Common in memory design
NOR as Universal Gate:
Verilog
6. XOR Gate
Implements logical XOR (Exclusive-OR) operation.
Truth Table:
Syntax:
xor instance_name (output, input1, input2, ... inputN);
Examples:
Verilog
Applications:
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- Half adder and full adder circuits
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- Parity generation and checking
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- Comparators
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- Data encryption
Properties:
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- Associative: A ⊕ B ⊕ C = (A ⊕ B) ⊕ C
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- Commutative: A ⊕ B = B ⊕ A
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- A ⊕ 0 = A
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- A ⊕ 1 = A'
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- A ⊕ A = 0
7. XNOR Gate
Implements logical XNOR (Exclusive-NOR) operation.
Truth Table:
Syntax:
xnor instance_name (output, input1, input2, ... inputN);
Examples:
Verilog
Applications:
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- Equality comparison
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- Even parity generation
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- Error detection
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11.1.2. Multi-Input Gates
All gates (except NOT) can have multiple inputs.
Example: 8-input AND gate
Verilog
11.1.3. Buffer and Inverter Primitives
1. BUF (Buffer)
Passes input to output without inversion.
Syntax:
buf instance_name (output, input);
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Usage:
Verilog
Applications:
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- Signal buffering
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- Drive strength enhancement
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- Fan-out management
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- Delay insertion
2. NOT (Detailed)
Multiple Output Capability:
Verilog
11.1.4. Tristate Gates
Tristate gates can output three states: logic 0, logic 1, and high-impedance (Z).
1. BUFIF1 (Buffer if 1)
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Output follows input when control is 1, otherwise high-impedance.
Truth Table:
Syntax:
bufif1 instance_name (output, input, control);
Example:
Verilog
2. BUFIF0 (Buffer if 0)
Output follows input when control is 0, otherwise high-impedance.
Truth Table:
Syntax:
bufif0 instance_name (output, input, control);
Example:
Verilog
3. NOTIF1 (Inverter if 1)
Inverts input when control is 1, otherwise high-impedance.
Truth Table:
Syntax:
notif1 instance_name (output, input, control);
4. NOTIF0 (Inverter if 0)
Inverts input when control is 0, otherwise high-impedance.
Truth Table:
Syntax:
notif0 instance_name (output, input, control);
11.1.5. Bidirectional Bus Example
Verilog
11.1.6. Gate Arrays and Vectors
Verilog allows instantiating multiple gates in a single statement.
Single Statement Multiple Instances
Verilog
Equivalent to:
and and_array0 (and_out[0], a[0], b[0]);
and and_array1 (and_out[1], a[1], b[1]);
and and_array2 (and_out[2], a[2], b[2]);
and and_array3 (and_out[3], a[3], b[3]);
Inverter Array Example
Verilog
11.1.7. Best Practices
1. Always Use Instance Names
Verilog
2. Use Appropriate Gate Types
Verilog
3. Document Gate Functions
Verilog
4. Use Gate Arrays for Repetitive Logic
Verilog
5. Handle Tristate Carefully
Verilog
6. Use Meaningful Wire Names
Verilog
11.1.8. Practical Examples
Example 1: 4-bit Parity Generator
Verilog
Example 2: Priority Encoder (4-to-2)
Verilog
Example 3: 1-bit Comparator
Verilog
Example 4: Full Subtractor
Truth Table:
Verilog
Example 5: SR Latch using NOR Gates
Verilog
Example 6: D Latch using Gates
Verilog
Example 7: 8-bit Bus Transceiver
Verilog