4.7 Keywords
When you step into the world of Verilog HDL (Hardware Description Language), one of the first things you'll notice is the use of specific keywords — reserved words that form the backbone of any Verilog design.
Keywords are special identifiers reserved to define the language constructs. Keywords are in lowercase.
These keywords are not just syntax; they define how digital circuits are described, simulated, and synthesized into real hardware. Whether you're writing a basic AND gate or modeling a pipelined processor, you’ll use these keywords as the foundation of your code.
Let’s explore what Verilog keywords are, why they matter, and the most essential ones every designer should know.
These keywords are used for:
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Declaring data types and signals
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Defining hardware modules and behaviours
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Controlling simulation and conditional logic
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Writing procedural and continuous assignments
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Handling time and delays
E.g., Module Definition and Hierarchy
Verilog
module u_op;
initial begin
$display (“This is VLSI Mentor E - Learning Platform.”);
//$display (“Here, users can learn VLSI Courses.”);
end
endmodule
Keyword
module
endmodule
initial
begin
end
$display
Description
Begins a module definition
Ends a module
Behavioural modeling basic building block
Start enclosing behavioural statements
End enclosing behavioural statements
System Task - Print statement