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17.1. Distributed Delay

Distributed delay places delay specifications throughout the code, at individual assignment statements. This is the most common approach for behavioral modeling.

Characteristics

Delays scattered throughout the code

Applied at each assignment statement

Easy to read and understand

Good for behavioral models

Can be harder to maintain

Basic Examples

Verilog

Distributed Delay in Behavioral Code

Verilog

Advantages and Disadvantages

ADVANTAGES:

Easy to understand - delays visible with logic

Flexible - different delays for different operations

Good for behavioral/RTL models

Simple to implement

DISADVANTAGES:

Delays mixed with functionality

Hard to maintain/update all delays

Not suitable for back-annotation

Difficult to disable for functional simulation

Delay modeling
types

Lumped delay

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