12.2. Switch Level Predefined Primitives

Basic MOS Primitives

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Verilog provides built-in primitives for transistor-level modeling:

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NMOS Switch

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nmos instance_name (drain, source, gate);

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PMOS Switch

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pmos instance_name (drain, source, gate);

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CMOS Transmission Gate

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cmos instance_name (output, input, ngate, pgate);

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Power Supply Primitives

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Supply1 - Power (VDD)

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supply1 vdd;  // Logic 1, highest drive strength

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Supply0 - Ground (GND)

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supply0 gnd;  // Logic 0, highest drive strength

 

Resistive MOS Primitives

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RNMOS - Resistive NMOS

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rnmos instance_name (drain, source, gate);

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// Reduced drive strength, models real transistor resistance

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RPMOS - Resistive PMOS

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rpmos instance_name (drain, source, gate);

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// Reduced drive strength

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RCMOS - Resistive CMOS

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rcmos instance_name (output, input, ngate, pgate);

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Pull Gates

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Pullup - Weak pull to 1

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pullup (signal);  // Weak logic 1

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Pulldown - Weak pull to 0

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pulldown (signal);  // Weak logic 0

 

12.2.1. NMOS and PMOS Behavior

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12.2.2. CMOS Logic Gates

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12.2.3 Transmission Gates

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12.2.4. Resistive MOS Switches

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