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14.7.1. Generate for Loop
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The generate for loop creates multiple instances of hardware in a regular, indexed pattern. It's the most commonly used generate construct for creating arrays of modules, gates, or other hardware elements.
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Syntax and Structure
Verilog
Key Components
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genvar: Generate variable (NOT a reg or wire). Exists only during elaboration.
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generate/endgenerate: Keywords to mark generate region
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begin : label end: Named block (REQUIRED for generate). Creates unique scope.
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Loop bounds: Must be constants or parameters (known at elaboration)
Basic Examples
Verilog
Module Instantiation in Generate
Verilog
Parameterized Generate
Verilog
Nested Generate for Loops
Verilog
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