3. RTL DESIGNING
RTL is just HDL code. Its full form is Register Transfer Logic. RTL can be written in any of the hardware languages such as Verilog HDL, VHDL, or System Verilog.
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Many academic level students have confusion about RTL term. Most of the time they hesitate in defining RTL term and its true meaning or intention.
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In very simple language, we can say that synthesizable HDL (Verilog) code is RTL. If HDL code is non-synthesizable then no need to call it RTL or no need to inbuilt RTL features in it, because RTL has some specific features through which it is accepted to be converted into hardware.
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We tried to differentiate the normal Verilog HDL code vs RTL Code. Don’t forget that RTL is also a Verilog HDL code but written with some specific features. Please refer below table for that:
DEFINITION
Verilog
Verilog
ASPECTS
PURPOSE
NORMAL VERILOG HDL CODE
RTL (Register Transfer Level) Code is a specific subset of Verilog code that describes the flow of data between registers and the logical operations performed on that data. It is used to describe the hardware implementation of a digital design.
It is not limited to describing hardware functionality but can also be used for simulation, testing, and high-level modeling.
RTL CODE
"Normal Verilog Code" is a broad term that refers to any code written in the Verilog hardware description language (HDL). It can be used for various purposes, including behavioral modeling, structural modeling, and testbench development.
RTL code is used to describe how data is transferred and processed in a digital system, making it suitable in synthesis (conversion into actual hardware like gates and flip-flops).
LEVEL OF ABSTRACTION
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Behavioral Level: Describes the functionality of a system without focusing on its hardware implementation (e.g., algorithms, high-level operations).
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Structural Level: Describes the interconnection of components or modules (e.g., gates, flip-flops, or other modules).
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Testbench Level: Used to verify the functionality of a design by providing input stimuli and checking outputs.
KEY FEATURES
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It uses any syntax from Verilog supported in LRM. There is no restriction on what to use for particular application.
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Designers can choose the logic as per their convenience
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Focuses on registers, combinational logic, and clocked sequential logic.
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Describes the behavior of a system in terms of clock cycles and data transfers.
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Uses clocked always blocks (always @ (posedge clk) for sequential logic.
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Describes combinational logic using continuous assignments (assign) or always blocks (always @(*)).
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Must be synthesizable, meaning it can be translated into actual hardware (gates, flip-flops, etc.).
EXAMPLE
//RTL Verilog Code
module adder (input clk, input [3:0] a, b,
output reg [3:0] sum);
always @(posedge clk) begin
sum <= a + b; //Data Transfer and
//addition at clock edge
end
endmodule
//Behavioral Verilog Code (not RTL)
module adder (input [3:0] a, b,
output reg [3:0] sum);
always @(*) begin
sum = a + b; //High-level addition
//without hardware details
end
endmodule
Below are some Key Differences between Normal Verilog Code and RTL Code:
ASPECTS
NORMAL VERILOG CODE
RTL CODE
PURPOSE
General-purpose (Simulation Modeling, testing)
Describes hardware for synthesis
ABSTRACTION LEVEL
Behavioral, Structural, or testbench level
Hardware focused
SYNTHESIZ-ABILITY
May or may not be synthesizable
Always synthesizable
FOCUS
Functionality or structure
Data flow between registers and logic
CLOCK USAGE
Not necessarily clocked
Explicitly uses clock signals
EXAMPLE USE CASE
Testbenches, high-level algorithms
Digital circuit design for FPGA/ASIC
RTL Code is a specific type of Verilog code used for hardware design and synthesis, while Normal Verilog Code is a broader term that includes RTL as well as other types of Verilog code used for simulation and modeling.
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In RTL (Register Transfer Level) design, the block diagram represents the flow of data between registers and the combinational logic that processes the data. It is a visual representation of how data is transferred and manipulated within a digital system, typically synchronized by a clock signal.
Here’s a breakdown of a typical RTL Design Block Diagram and its components:
input
Combinational
Logic Block - 1
Registers
(Flip-flops)
clock
Combinational
Logic Block - 2
output
Key Components of Block Diagram:
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1. Inputs and Outputs:
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Inputs: Data signals that enter the system.
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Outputs: Processed data signals that leave the system.
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2. Combinational Logic Blocks:
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These blocks perform logical operations on the input data (e.g., addition, subtraction, AND, OR etc.).
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They do not have memory and produce outputs based solely on the current inputs.
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Examples: Arithmetic Logic Units (ALUs), multiplexers, decoders.
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3. Registers (Flip-Flops):
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Registers store data temporarily and are synchronized with a clock signal.
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They hold the output of combinational logic until the next clock cycle.
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Examples: D Flip-Flops, Shift Registers.
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4. Clock Signal:
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The clock synchronizes the transfer of data between registers.
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Data is transferred only at the rising or falling edge of the clock.
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5. Data Path:
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The flow of data from input to output through combinational logic and registers.
Example - 1: RTL Design of a Simple 4-Bit Adder
A, B
4-bit Adder Combinational
Logic Block - 1
4-bit Registers
(Flip-flops)
clock
Combinational
Logic Block - 2
SUM
Description:
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Inputs: Two 4-bit inputs A and B.
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Combinational Logic: A 4-bit adder performs the addition of A and B.
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Register: The result of the addition is stored in a 4-bit register at the clock edge.
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Output: The registered sum is available as the output.
Verilog
module rtl_adder (
input clk, //CLOCK SIGNAL
input [3:0] A, B, //4-BIT INPUTS
output reg [3:0] SUM //4-BIT OUTPUT (REGISTERED)
);
//COMBINATIONAL LOGIC
wire [3:0] adder_out;
assign adder_out = A + B;
//REGISTER (FLIP-FLOP)
always @(posedge clk) begin
SUM <= adder_out; //STORE THE RESULT IN A REGISTER AT THE CLOCK EDGE
end
endmodule
KEY TAKEAWAYS
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The RTL block diagram visually represents the flow of data between combinational logic and registers.​
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Combinational logic performs operations, while registers store data temporarily.
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The clock signal synchronizes data transfer and ensures proper timing in the design.
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RTL designs are used to create synthesizable hardware for FPGAs and ASICs.
Example - 2: 4-BIT COUNTER WITH ENABLE AND RESET
reset
enable
4-Bit Counter
clock
SUM
Description:
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This design implements a 4-bit counter that increments its value on every clock cycle when enabled.
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It has a reset signal to initialize the counter to 0 and an enable signal to control counting.
Verilog
module rtl_adder (
input clk, //CLOCK SIGNAL
input reset, enable, //ACTIVE-HIGH RESET, ENABLE
output [3:0] SUM //4-BIT OUTPUT (REGISTERED)
);
reg [3:0] count;
// Counter logic
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000; //RESET COUNTER TO 0
else if (enable)
count <= count + 1; //INCREMENT COUNTER IF ENABLED
end
assign SUM = count;
endmodule
Example - 3: 8-BIT SHIFT REGISTER WITH PARALLEL LOAD
DATA
LOAD
SHIFT
PARALLEL LOAD LOGIC
SHIFT LOGIC
8-bit SHIFT REGISTERS
(FLIP-FLOPS)
clock
SUM
Description:
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This design implements an 8-bit shift register that can either:
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LOAD parallel data when the load signal is high.
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SHIFT data serially when the shift signal is high.
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The serial output is the least significant bit (LSB) of the register.
Verilog
module shift_register_8bit (
input clk, // CLOCK SIGNAL
input reset, // ACTIVE-HIGH RESET
input load, // ACTIVE-HIGH PARALLEL LOAD
input shift, // ACTIVE-HIGH SHIFT ENABLE
input [7:0] data_in, // PARALLEL INPUT DATA
output reg serial_out // SERIAL OUTPUT
);
reg [7:0] reg_data; // 8-BIT REGISTER SHIFT REGISTER LOGIC
always @(posedge clk or posedge reset) begin
if (reset)
reg_data <= 8'b00000000; // RESET REGISTER TO 0
else if (load)
reg_data <= data_in; // LOAD PARALLEL DATA
else if (shift)
reg_data <= {reg_data[6:0], 1'b0}; // SHIFT LEFT (LSB OUT)
end
// SERIAL OUTPUT IS THE LSB OF THE REGISTER
assign serial_out = reg_data[7];
endmodule
Example - 4: SIMPLE ARITHMETIC LOGIC UNIT (ALU)
A, B
OP
ALU LOGIC
(ADD, SUB, AND, OR)
SHIFT
OUTPUT REGISTER (OPTIONAL)
RESULT
Description:
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This design implements a simple 4-bit ALU that performs the following operations:
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Addition (A + B)
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Subtraction (A - B)
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Bitwise AND (A & B)
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BITWISE OR (A | B)
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The operation is selected using a 2-bit OP signal.
Verilog
module alu_4bit (
input clk, // CLOCK SIGNAL
input [1:0] op, // OPERATION SELECT (2 BITS)
input [3:0] A, B, // 4-BIT INPUTS
output reg [3:0] result // 4-BIT RESULT
);
// ALU LOGIC
always @(posedge clk) begin
case (op)
2'b00: result <= A + B; // ADDITION
2'b01: result <= A - B; // SUBTRACTION
2'b10: result <= A & B; // BITWISE AND
2'b11: result <= A | B; // BITWISE OR
default: result <= 4'b0000; // DEFAULT CASE
endcase
end
endmodule
Example - 5: MEALY FSM FOR A SEQUENCE DETECTOR (DETECTING "101")
STATE TRANSITION TABLE
CURRENT STATE INPUT NEXT STATE OUTPUT
S0 0 S0 0
S0 1 S1 0
S1 0 S2 0
S1 1 S1 0
S2 0 S0 0
S2 1 S1 1
Verilog
module sequence_detector_101 (
input clk, // CLOCK SIGNAL
input reset, // ACTIVE-HIGH RESET
input data_in, // INPUT BIT STREAM
output reg detected // OUTPUT: 1 WHEN "101" IS DETECTED
);
// STATE ENCODING
typedef enum {S0, S1, S2} state_t;
state_t current_state, next_state;
// STATE TRANSITION LOGIC
always @(posedge clk or posedge reset) begin
if (reset) begin
current_state <= S0;
end else begin
current_state <= next_state;
end
end
// NEXT STATE AND OUTPUT LOGIC (MEALY MACHINE)
always @(*) begin
case (current_state)
S0: begin
if (data_in == 1) begin
next_state = S1;
detected = 0;
end else begin
next_state = S0;
detected = 0;
end
end
S1: begin
if (data_in == 0) begin
next_state = S2;
detected = 0;
end else begin
next_state = S1;
detected = 0;
end
end
S2: begin
if (data_in == 1) begin
next_state = S1;
detected = 1;
end else begin
next_state = S0;
detected = 0;
end
end
endcase
end
endmodule
KEY TAKEAWAYS​
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FSMs are used to model systems with a finite number of states and transitions.​
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Moore Machines have outputs dependent only on the current state.​
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Mealy Machines have outputs dependent on the current state and inputs.​
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The block diagram of an FSM consists of:​
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Combinational Logic for next state and output.​
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State Register to store the current state.​​
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Clock for synchronization.