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15.2. Tasks
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A task is a more powerful procedural block that can have zero, one, or multiple outputs. Tasks can consume simulation time, contain timing controls, and call other tasks or functions. They are ideal for testbench operations and complex procedures.
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Task Syntax and Structure
Verilog
Key Characteristics
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Can have ZERO, ONE, or MULTIPLE outputs
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Can have input, output, and inout arguments
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CAN contain timing controls (#, @, wait)
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Can consume simulation time
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Can call other tasks and functions
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Can have local variables
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Called as a statement (not an expression)
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Basic Task Examples
Verilog
Tasks with Timing Controls
Verilog
Tasks Calling Other Tasks and Functions
Verilog
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