9.2 Module Instantiation
What is Module Instantiation?
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Module instantiation is the process of creating an instance of a module within another module. This allows you to build hierarchical designs by connecting smaller modules together to create more complex systems.
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9.2.1. Types of Module Instantiation
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9.2.1.1. Named Port Connection (Recommended)
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This method explicitly connects ports by name, making the code more readable and maintainable:
Verilog
Advantages:
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- Easy to read and understand
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- Order of ports doesn't matter
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- Less prone to errors during maintenance
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- Self-documenting code
9.2.1.2. Positional Port Connection
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Ports are connected based on their position in the module declaration:
Verilog
Disadvantages:
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- Error-prone if port order changes
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- Difficult to maintain
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- Not recommended for modules with many ports
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9.2.1.3. Mixed Connection Style
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SystemVerilog allows mixing both styles (but not recommended):
Verilog
9.2.2. Multiple Instantiation
Creating multiple instances of the same module:
Verilog
9.2.3. Array of Instances (Generate Blocks)
For regular structures, use generate blocks:
Verilog