9.2 Module Instantiation
What is Module Instantiation?
Module instantiation is the process of creating an instance of a module within another module. This allows you to build hierarchical designs by connecting smaller modules together to create more complex systems.
9.2.1. Types of Module Instantiation
9.2.1.1. Named Port Connection (Recommended)
This method explicitly connects ports by name, making the code more readable and maintainable:
Verilog
Advantages:
- Easy to read and understand
- Order of ports doesn't matter
- Less prone to errors during maintenance
- Self-documenting code
9.2.1.2. Positional Port Connection
Ports are connected based on their position in the module declaration:
Verilog
Disadvantages:
- Error-prone if port order changes
- Difficult to maintain
- Not recommended for modules with many ports
9.2.1.3. Mixed Connection Style
SystemVerilog allows mixing both styles (but not recommended):
Verilog
9.2.2. Multiple Instantiation
Creating multiple instances of the same module:
Verilog
9.2.3. Array of Instances (Generate Blocks)
For regular structures, use generate blocks:
Verilog