14.6. Introduction to Loops in Verilog
Loops provide a mechanism to execute a block of code repeatedly. In Verilog, loops are essential for testbench development, array initialization, and repetitive operations in behavioral models. Understanding when and how to use each loop type is crucial for both simulation and synthesis.
Types of Loops
Verilog provides four types of loops:
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for loop - Counter-controlled iteration (most common)
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while loop - Condition-controlled iteration (pre-test)
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repeat loop - Fixed number of iterations
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forever loop - Infinite loop (testbench only)
Loop Applications
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Critical Synthesizability Note
⚠ CRITICAL: Most loops are NOT synthesizable! Only FOR loops with CONSTANT bounds and known iteration counts can sometimes be synthesized (unrolled). while, repeat, and forever loops are TESTBENCH ONLY.
14.6.1. For Loop
14.6.2. While Loop
14.6.3. Repeat Loop
14.6.4. Forever Loop
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