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17.3. Pin-to-Pin Delays
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Pin-to-pin delays (also called path delays) specify delays from specific input pins to specific output pins. They are defined in specify blocks and provide the most accurate timing model.
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Characteristics
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Defined in specify blocks
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Specify exact paths from inputs to outputs
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Support different delays for different paths
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Enable SDF back-annotation
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Support conditional and edge-sensitive delays
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Most accurate timing model
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Basic Syntax
Verilog
Types of Pin-to-Pin Delays
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Comprehensive Examples
Verilog
Advantages and Disadvantages
ADVANTAGES:
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Most accurate timing model
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Complete separation of timing and logic
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Support for SDF back-annotation
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Path-specific delays
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Timing checks integration
DISADVANTAGES:
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More complex to write
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Requires understanding of specify blocks
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More verbose
Comparison of Delay Models
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