8.2. Random Number Generation: $random
The `$random` function generates pseudo-random numbers for creating diverse test stimuli and building robust verification environments.
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8.2.1 Basic Syntax
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Returns: 32-bit signed integer (-2,147,483,648 to 2,147,483,647)
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Syntax:
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integer value;
value = $random; // Uses internal seed
value = $random(seed); // Uses provided seed
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8.2.2 Generating Constrained Random Values
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Problem: `$random` returns full 32-bit range, but we often need specific ranges.
Solution: Use modulo arithmetic and handle negative values.
Verilog
module random_range_demo;
integer rand_val, seed;
integer min, max;
integer i;
initial begin
seed = 42; // For reproducibility
// Generate random value in range [0:15]
$display("Random values in range [0:15]:");
for (i = 0; i < 5; i = i + 1) begin
rand_val = $random(seed) % 16;
if (rand_val < 0) rand_val = -rand_val; // Handle negative
$display(" %0d", rand_val);
end
// Generate random value in range [min:max]
min = 100; max = 200;
$display("\nRandom values in range [%0d:%0d]:", min, max);
for (i = 0; i < 5; i = i + 1) begin
rand_val = $random(seed) % (max - min + 1);
if (rand_val < 0) rand_val = -rand_val;
rand_val = rand_val + min;
$display(" %0d", rand_val);
end
end
endmodule
8.2.3 Practical Application: Random Test Vector Generation
Verilog
module alu_random_test;
reg [7:0] operand_a, operand_b;
reg [2:0] operation;
reg [8:0] result;
integer seed, i;
// Simple ALU operations
always @(*) begin
case (operation)
3'd0: result = operand_a + operand_b;
3'd1: result = operand_a - operand_b;
3'd2: result = operand_a & operand_b;
3'd3: result = operand_a | operand_b;
3'd4: result = operand_a ^ operand_b;
3'd5: result = ~operand_a;
default: result = 0;
endcase
end
initial begin
seed = 99; // Reproducible tests
$display("ALU Random Test Suite");
$display("=====================");
for (i = 0; i < 10; i = i + 1) begin
// Generate random inputs
operand_a = $random(seed);
operand_b = $random(seed);
operation = $random(seed) % 6; // 0-5 operations
#1; // Wait for combinational logic
$display("Test %0d: A=0x%h, B=0x%h, OP=%0d => Result=0x%h",
i, operand_a, operand_b, operation, result);
end
$display("=====================");
$display("Random tests completed!");
end
endmodule
8.2.4 Random Delay Generation
Verilog
module random_delay_demo;
reg request, acknowledge;
integer delay, seed, i;
initial begin
seed = 55;
request = 0;
for (i = 0; i < 5; i = i + 1) begin
// Random delay between 10-50 time units
delay = 10 + ($random(seed) % 41);
if (delay < 10) delay = delay + 10;
$display("Iteration %0d: Waiting %0d time units", i, delay);
#delay request = ~request;
end
end
endmodule
Key Points About $random
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