17. Introduction to Delay Modeling
Delay modeling in Verilog is the representation of signal propagation time through hardware components. Accurate delay modeling is essential for timing simulation, verification, and ensuring that designs meet timing constraints in real hardware.
Why Delay Modeling?
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Timing Accuracy: Simulate real hardware propagation delays
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Verification: Detect setup/hold violations, race conditions
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Performance Analysis: Determine maximum operating frequency
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Power Estimation: Dynamic power depends on transitions
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STA Support: Enable static timing analysis
Types of Delays in Verilog
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Inertial Delay: Default in Verilog, filters glitches
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Transport Delay: Propagates all transitions (not standard)
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Rise/Fall Delays: Different delays for 0→1 and 1→0
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Turn-on/Turn-off: Delays for tri-state transitions
Delay Specification Formats
Verilog
Types of Delay Models
Verilog supports three primary delay modeling approaches, each suited for different levels of abstraction and accuracy requirements.
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17.1. Distributed Delay
17.2. Lumped Delay
17.3. Pin-to-Pin Delay
17.4. Specify Block