5.1.1 wire & tri nets
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The wire and tri nets connect the digital elements. A wire net can be used to model the nets which are driven by a single gate or continuous assignment while a tri net can be driven by multiple drivers.
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The default value of wire and tri is 1'bz.
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Multiple drivers driving the wire and tri at same time with different value and same strength provides ‘x’ resultant.
What is the key difference between wire and tri? How wire is single driven and tri is multiple driven?
It is mentioned at many Verilog resources that wire can have only single driver which means that wire can be assigned only once at one instant of time. This is pretty clear about single driven functionality of wire.
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Please refer the below Verilog HDL code for more clarity of this wire behaviour:
Verilog
module vlsimentor;
wire in1, in2;
wire y;
assign y = in1;
assign y = in2;
initial begin
$monitor($time, " | in1 = %b, in2 = %b, y = %b", in1, in2, y);
in1 = 0; in2 = 0;
#5 in1 = 0; in2 = 1;
#5 in1 = 1; in2 = 0;
#5 in1 = 1; in2 = 1;
end
endmodule
Output
0 | in1 = 0, in2 = 0, y = 0
5 | in1 = 0, in2 = 1, y = x
10 | in1 = 1, in2 = 0, y = x
15 | in1 = 1, in2 = 1, y = 0
In the above code, in1 and in2 are assigned to wire y at same time which is not correct as per the single driven functionality of wire. This will not give compilation or any other error. This will provide unexpected value at wire y.
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This type of situation is called as signal contention where two wires are connected to a third wire. This will lead to ambiguity error.
Ambiguity is "to be open for more than one interpretation". There can be any of two values in1 or in2 on wire y but can't be sure which value takes precedence. This is called Ambiguity or Race Condition or Metastability.
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Pictorial representation of above code:
SIGNAL CONTENTION
This is an assumption that as tri net is multiple driven so above contention should get resolved by using tri instead of wire.
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Please see below code:
Verilog
module vlsimentor;
wire in1, in2;
tri y;
assign y = in1;
assign y = in2;
initial begin
$monitor($time, " | in1 = %b, in2 = %b, y = %b", in1, in2, y);
in1 = 0; in2 = 0;
#5 in1 = 0; in2 = 1;
#5 in1 = 1; in2 = 0;
#5 in1 = 1; in2 = 1;
end
endmodule
Is this code correct?
Absolutely No, above contention will remain even if we use tri because this is the problem with real hardware wire.
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See the output of above code below:
Output
0 | in1 = 0, in2 = 0, y = 0
5 | in1 = 0, in2 = 1, y = x
10 | in1 = 1, in2 = 0, y = x
15 | in1 = 1, in2 = 1, y = 1
This contention will get resolved after using the strength mechanism. We will discuss strength later. First, lets discuss tri net.
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The "tri" net is used to model the tri-state buffers.
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E.g., bufif0, bufif1, notif0, notif1
This complete circuit refers to tri net. Even nets used in this circuit are wire only. You can use tri also instead of wires.
Hence, there is no as such difference between wire and tri except wires are used for connectivity and tri is used to model tri-state circuits.
Recommendation
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Be careful when writing a Verilog HDL model that any of wire is connected to single source only. This prevents signal contention.