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14.7.2. Generate if Statement
The generate if statement conditionally includes or excludes hardware based on parameter values evaluated at elaboration time. This enables configuration-dependent designs where different hardware is instantiated based on parameters.
Syntax and Structure
Verilog
Key Characteristics
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Condition must be constant expression (parameters/constants)
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Evaluated at elaboration time, not simulation time
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Only ONE branch is elaborated (TRUE or FALSE)
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else is optional
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Named blocks (labels) are REQUIRED
Basic Examples
Verilog
if-else-if Ladder
Verilog
Nested Generate if
Verilog
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