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14.7.2. Generate if Statement

The generate if statement conditionally includes or excludes hardware based on parameter values evaluated at elaboration time. This enables configuration-dependent designs where different hardware is instantiated based on parameters.

Syntax and Structure

Verilog

Key Characteristics

Condition must be constant expression (parameters/constants)

Evaluated at elaboration time, not simulation time

Only ONE branch is elaborated (TRUE or FALSE)

else is optional

Named blocks (labels) are REQUIRED

Basic Examples

Verilog

if-else-if Ladder

Verilog

Nested Generate if

Verilog

Generate for

Generate case

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