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5.1 Physical/Net Data Types

  • Net is not a keyword but represents a class of data types which are used as wire in digital hardware circuits. 

 

  • Net represents connection between hardware components. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to.

 

  • In the below Figure 2.1, Input-1, 2 and Output signals are nets which are continuously driven by some source. For instance, Output net is continuously driven by nets Input-1, 2 with the value Input1 & Input2.

image.png

Figure 2.1: Nets driving net

  • Nets are declared primarily with the keyword wire. The term wire and net are often used interchangeably. Nets get the output value of their drivers. If net has no driver, it gets the value z.

 

  • Default value is z (except the trireg net, which defaults to x).

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  • Default size is 1-bit (can be explicitly declared as vector).

 Verilog

wire Output; // Declare net for above circuit.

wire Input1, Input2; // Declare two wires for the above circuit.

wire n1 = 1’b0; // Wire n1 is fixed to logic value 0 at declaration.

        -    wire               |           Net with single driver                                          |           Default Value = 1'bz

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        -    tri                  |           Net with multiple driver                                       |           Default Value = 1'bz

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        -    tri0                |           Pulls down the net at gate level                            |           Default Value = 1'b0

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        -    tri1                |           Pulls up the net at gate level                                |           Default Value = 1'b1

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        -    wor                |           Model wired logic OR function at gate level            |           Default Value = 1'bz

                                               Performs OR operation on multiple driver logic

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        -    wand             |           Model wired logic AND function at gate level           |           Default Value = 1'bz

                                              Performs AND operation on multiple driver logic

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        -    trior               |           Model wired logic OR function at gate level             |           Default Value = 1'bz

                                               Performs OR operation on multiple driver logic

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        -    triand             |           Model wired logic AND function at gate level           |           Default Value = 1'bz

​                                               Performs AND operation on multiple driver logic

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        -    trireg              |           Stores the value at previous level (gate)                |           Default Value = 1'bx

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        -    supply0           |           Use to model power supply in the circuit                |           Default Value = 1'b0

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        -    supply1           |           Use to model power supply in the circuit                |           Default Value = 1'b1

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        -    uwire              |           Unresolved or unidriver wire                                  |           Default Value = 1'bz

Following are the net data type variables:

5.1.1 wire & tri nets​

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5.1.2 Signal Strengths

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5.1.3 wired nets

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5.1.4 trireg net

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5.1.5 tri0 & tri1 nets

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5.1.6 supply0 & supply1

Data types

Wire & tri nets

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