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14.6.2. While Loop
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The while loop is a condition-controlled loop that executes as long as the specified condition is true. It is a PRE-TEST loop (condition checked before execution) and is NOT synthesizable.
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Syntax and Structure
Verilog
Characteristics
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Condition is checked BEFORE each iteration
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If condition is false initially, loop never executes
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Iteration count unknown until runtime
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NOT synthesizable (testbench only)
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Must have timing control to avoid infinite zero-time loop
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Basic Examples
Verilog
While Loop vs For Loop Equivalence
Verilog
Common While Loop Patterns
Verilog
Critical: Avoiding Infinite Loops
âš DANGER: While loops without timing controls will create INFINITE ZERO-TIME LOOPS that hang the simulator!
Verilog
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