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14.4.2. Event-Based Timing Controls
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Event-based timing controls use the @ symbol to detect signal transitions or changes. These are the ONLY timing controls that are synthesizable when used properly in RTL design.
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14.4.2.1 Edge-Sensitive Event Controls
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posedge (Positive Edge)
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Triggers when signal transitions from 0 to 1 (or X to 1, Z to 1).
Verilog
negedge (Negative Edge)
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Triggers when signal transitions from 1 to 0 (or X to 0, Z to 0).
Verilog
Edge Detection Transitions
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14.4.2.2 Level-Sensitive Event Control (OR-ing Events)
Single Signal Change
Verilog
Multiple Signals (OR Sensitivity)
Verilog
Mixed Edge and Level Events
Verilog
14.4.2.3 Named Events
Named events provide a way to trigger execution without using signals.
Declaration and Triggering
Verilog
Practical Example
Verilog
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