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14.5.2. Case Statements
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The case statement provides a clean way to implement multi-way branching based on the value of an expression.
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Unlike if-else ladders, case statements evaluate all branches in PARALLEL and select the matching branch.
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Basic case Statement
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Syntax
Verilog
Key Characteristics
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Parallel evaluation (not sequential like if-else)
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Only ONE branch executes (first match)
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default is optional but HIGHLY recommended
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Exact bit-by-bit comparison (X and Z compared)
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Multiple values can map to same statement
Simple Examples
Verilog
Multiple Values for Same Branch
Verilog
14.5.2.1. casex and casez - Don't Care Matching
casez Statement
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casez treats ? and Z as don't care bits in BOTH expression and case items.
Verilog
casex Statement
casex treats ?, X, and Z as don't care bits in BOTH expression and case items.
Verilog
Comparison: case vs casez vs casex
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âš WARNING: casex can mask X values from bugs! Use casez preferably, and case when possible.
14.5.2.2. Full Case and Parallel Case
Full Case
A case statement is FULL if all possible values of the expression are covered. If not full, unspecified values take default (or create latches).
Verilog
Parallel Case
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A case statement is PARALLEL if no two case items can match simultaneously. If not parallel, priority is determined by order (first match wins).
Verilog
Comparison: If/Else vs Case
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