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14.6.1. For Loop
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The for loop is the most commonly used loop in Verilog. It provides a compact syntax for counter-controlled iteration and is the ONLY loop with limited synthesizability.
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Syntax and Structure
Verilog
Components
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Initialization: Executed once at the start (e.g., i = 0)
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Condition: Checked before each iteration (e.g., i < 10)
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Increment/Decrement: Executed after each iteration (e.g., i = i + 1)
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Basic Examples
Verilog
14.6.1.1. Advanced For Loop Usage
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Multiple Statements in Loop Body
Verilog
Nested For Loops
Verilog
Variable Step Size
Verilog
14.6.1.2. Synthesizable For Loops
IMPORTANT: For loops can be synthesized ONLY if the iteration count is KNOWN at elaboration time (constant bounds). The loop is 'unrolled' into replicated hardware.
Synthesizable Example
Verilog
Non-Synthesizable Example
Verilog
Common For Loop Patterns
Verilog
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