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14.7.4. Advanced Generate Techniques
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Combining Generate Types
Verilog
Best Practices and Guidelines
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General Best Practices
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Always use genvar for generate loop variables
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Always provide unique labels for generate blocks
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Use parameters for generate conditions
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Include default in generate case
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Document what each configuration does
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Keep generate blocks simple and readable
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Naming Conventions
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Use descriptive labels: adder_gen not g1
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Use _gen suffix for generate loops
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Use meaningful names for genvar: i, j, k or bit, stage
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Common Pitfalls to Avoid
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Don't use reg/wire as loop variable - use genvar
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Don't forget begin:label end blocks
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Don't use non-constant expressions in conditions
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Don't create generate without generate/endgenerate keywords
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Don't reuse label names in the same module
Common Mistakes and Solutions
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Mistake #1: Missing Labels
Verilog
Mistake #2: Using integer Instead of genvar
Verilog
Mistake #3: Variable Loop Bounds
Verilog
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