12.2.2. CMOS Logic Gates
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CMOS Inverter (NOT Gate)
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The most fundamental CMOS gate - one PMOS and one NMOS.
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Circuit Diagram:
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Verilog
Truth Table:
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Operation:
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1. A = 0:
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- PMOS conducts (gate=0) → Y connected to VDD → Y=1
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- NMOS off (gate=0) → No path to GND
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2. A = 1:
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- PMOS off (gate=1) → No path to VDD
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- NMOS conducts (gate=1) → Y connected to GND → Y=0
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Key Points:
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- No static current: Never both ON simultaneously
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- Full swing: Output is either VDD or GND (strong 0 and 1)
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- Complementary: PMOS and NMOS work together
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CMOS NAND Gate (2-Input)
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Circuit:
.png)
Verilog
Truth Table:
.png)
Key Insight:
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- PMOS Parallel: ANY input LOW → output HIGH
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- NMOS Series: BOTH inputs HIGH → output LOW
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- Result: NAND function
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Testbench:
Verilog
CMOS NOR Gate (2-input)
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Circuit Diagram:
.png)
Verilog
Truth Table:
.png)
Key Insight:
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- PMOS Series: BOTH inputs LOW → output HIGH
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- NMOS Parallel: ANY input HIGH → output LOW
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- Result: NOR function
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CMOS AND Gate
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AND Gate = NAND + Inverter
Verilog
CMOS AND Gate
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OR Gate = NOR + Inverter
Verilog
CMOS AND Gate
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OR Gate = NOR + Inverter
Verilog
Complete CMOS Gate Library
Verilog