12.2.2. CMOS Logic Gates
CMOS Inverter (NOT Gate)
The most fundamental CMOS gate - one PMOS and one NMOS.
Circuit Diagram:
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Verilog
Truth Table:
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Operation:
1. A = 0:
- PMOS conducts (gate=0) → Y connected to VDD → Y=1
- NMOS off (gate=0) → No path to GND
2. A = 1:
- PMOS off (gate=1) → No path to VDD
- NMOS conducts (gate=1) → Y connected to GND → Y=0
Key Points:
- No static current: Never both ON simultaneously
- Full swing: Output is either VDD or GND (strong 0 and 1)
- Complementary: PMOS and NMOS work together
CMOS NAND Gate (2-Input)
Circuit:
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Verilog
Truth Table:
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Key Insight:
- PMOS Parallel: ANY input LOW → output HIGH
- NMOS Series: BOTH inputs HIGH → output LOW
- Result: NAND function
Testbench:
Verilog
CMOS NOR Gate (2-input)
Circuit Diagram:
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Verilog
Truth Table:
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Key Insight:
- PMOS Series: BOTH inputs LOW → output HIGH
- NMOS Parallel: ANY input HIGH → output LOW
- Result: NOR function
CMOS AND Gate
AND Gate = NAND + Inverter
Verilog
CMOS AND Gate
OR Gate = NOR + Inverter
Verilog
CMOS AND Gate
OR Gate = NOR + Inverter
Verilog
Complete CMOS Gate Library
Verilog