top of page
12.4 D Latch using CMOS
​
Verilog Implementation:
Verilog
Testbench:
Verilog
Example 2: Tristate Buffer using CMOS
​
Verilog Implementation:
Verilog
Example 3: SRAM Cell (6T) using CMOS
​
Verilog Implementation:
Verilog
Example 4: Dynamic Logic Gate
​
Verilog Implementation:
Verilog
bottom of page