4.3 OPERATOR USAGE
Operators perform operations on operands.
Operator: The operation which is to be performed.
Operand: The operation on which to be performed.
e.g.,
a + b
The variables `a` and `b` are operands.
The symbol `+` is operator.
There are three kinds of operators available in Verilog HDL which are given below:​​​​​​
4.3.1. Unary Operator: work on single operand.
Verilog
module u_op;
reg a;
initial begin
if (!a) begin // ! is a unary operator
$display (“This is Unary Operator example”);
end
end
initial begin
a = 0;
end
endmodule
Output
This is Unary Operator example.
4.3.2. Binary Operator: work on two operands.
Verilog
module b_op;
reg a, b = 0, c = 1;
initial begin
$display (“a = %b”, a);
end
initial begin
a = b & c; // & is binary operator
end
endmodule
Output
a = 0
4.3.3. Ternary Operator: work on three operands.
Verilog
module wh_sp;
reg a, b, s; wire y;
assign y = (s == 0) ? a : b; // ()?: is ternary operator
initial begin
$monitor (“a = %b, b = %b, s = %b, y = %b”, a, b, s, y);
a = 1; b = 0; s = 0;
a = 0; b = 0; s = 0;
a = 0; b = 1; s = 1;
a = 0; b = 0; s = 1;
end
endmodule
Output
a = 1, b = 0, s = 0, y = 1
a = 1, b = 0, s = 0, y = 0
a = 1, b = 0, s = 0, y = 1
a = 1, b = 0, s = 0, y = 0