11.2. Gate-Level Delays
Timing is everything in digital design. Gate-level delays are crucial for accurate simulation, timing verification, and understanding how your design will behave in real silicon. Without proper delay modeling, simulations can give misleading results that don't match hardware behavior.
11.2.1. Understanding Delays
A delay is the time taken for a change at the input to propagate to the output.
Verilog
Simulation Timeline:
Time = 0ns: a=0, b=0, y=0
Time = 10ns: a=1, b=1
Time = 10ns: y=0 (still old value)
Time = 15ns: y=1 (delay of 5ns)
11.2.1.1. Why Model Delays?
1. Realistic Simulation
Verilog
2. Race Condition Detection
Verilog
3. Critical Path Analysis
Verilog
11.2.2. Types of Gate Delays
Detailed Explanation
Rise Delay (`tpLH` - Low to High):
Time for output to transition from 0 to 1.
Fall Delay (`tpHL` - High to Low):
Time for output to transition from 1 to 0.
Turn-off Delay (`tpHZ`/`tpLZ`):
Time for output to enter high-impedance state.
11.2.2.1. Lumped Delay (Single Value)
Same delay for all transitions.
Syntax:
gate #delay instance_name (output, inputs);
Example:
Verilog
Behavior:
- 0→1 transition: 5ns delay
- 1→0 transition: 5ns delay
- Any transition: 5ns delay
11.2.2.2. Separate Rise and Fall Delays
Different delays for rising and falling transitions.
Syntax:
gate #(rise_delay, fall_delay) instance_name (output, inputs);
Example:
Verilog
Simulation:
Time = 0ns: y = 0
Time = 10ns: Input changes to make y=1
Time = 13ns: y = 1 (rise delay = 3ns)
Time = 20ns: Input changes to make y=0
Time = 25ns: y = 0 (fall delay = 5ns)
11.2.2.3. Full Delay Specification (Rise, Fall, Turn-off)
For tristate gates: rise, fall, and turn-off delays.
Syntax:
gate #(rise, fall, turnoff) instance_name (output, input, control);
Example:
Verilog
Transitions:
- Z→1: rise delay (3ns)
- Z→0: fall delay (4ns)
- Any→Z: turn-off delay (2ns)
- 0→1: rise delay (3ns)
- 1→0: fall delay (4ns)
Complete Example
Verilog
Testbench:
Verilog
11.2.3. Min:Typ:Max Delays
Real circuits have delay variations due to:
- Process variations (P)
- Voltage variations (V)
- Temperature variations (T)
Syntax
gate #(min:typ:max) instance_name (output, inputs);
// Or with rise/fall:
gate #(rise_min:rise_typ:rise_max, fall_min:fall_typ:fall_max)
instance_name (output, inputs);
Example: PVT Corners
Verilog
Simulation with Different Corners
Verilog
11.2.4. Best Practices
1. Always Model Realistic Delays
// ❌ Avoid zero-delay models for timing verification
and and1 (y, a, b);
// ✅ Use realistic delays
and #(2.0, 2.5) and1 (y, a, b);
2. Use Min:Typ:Max for Corners
// ✅ Model PVT variations
and #(1.5:2.0:3.0, 2.0:2.5:3.5) and1 (y, a, b);
3. Document Critical Paths
Verilog
4. Use SDF for Gate-Level Simulation
Verilog
5. Check Timing Violations
Verilog