5.1.4 trireg nets
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The trireg net is used to model capacitive wires. It stores the previous driven value. It works in two different states:
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Driven State When at least one driver drives it with any value among 1, 0, x.​​
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Capacitive State When all the drivers drive with high impedance ‘z’ value.
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Strength of value on trireg in a capacitive state can be small, medium, or large.
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Strength of value on trireg in driven state can be supply, strong, pull, or weak.
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In the above diagram, and gate is connected to wire c if wire a is 1. The wire c is connected to trireg d if wire b is high.
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Let’s verify the capacitive capability of trireg d in this diagram.
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Case-1:
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Case-2:
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Below is an example describing the working of trireg net using Verilog HDL code:
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Assignment on normal wire:
Verilog
module sdv(in1, ctrl, y);
input in1, ctrl;
output y; //Default data type of output port is wire.
wire y; //Optional - because of above comment
assign y = ctrl ? in1 : 1’bz;
endmodule
Output
When ctrl = 1, y = in1
When ctrl = 0, y = 1'bz
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Assignment on trireg wire:
Verilog
module sdv(in1, ctrl, y);
input in1, ctrl;
output y; //Default data type of output port is wire.
trireg y; //Optional - because of above comment
assign y = ctrl ? in1 : 1’bz;
endmodule
Output
When ctrl = 1, y = in1
When ctrl = 0, y = previous value of in1
Further Example
This is the explanation of above CMOS circuit:
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The capacitive strength of trireg_la net is large, trireg_me1 and trireg_me2 are medium, and trireg_sm is small. Simulation reports the following sequence of events:
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At simulation time 0, wire a and wire b have a value of 1. The wire c drives a value of 1 into trireg_la and trireg_sm; wire d drives a value of 1 into trireg_me1 and trireg_me2.
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At simulation time 10, the value of wire b changes to 0, disconnecting trireg_sm and trireg_me2 from their drivers. These trireg nets enter the capacitive state and store the value 1, their last driven value.
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At simulation time 20, wire c drives a value of 0 into trireg_la.
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At simulation time 30, wire d drives a value of 0 into trireg_me1.
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At simulation time 40, the value of wire a change to 0, disconnecting trireg_la and trireg_me1 from their drivers. These trireg nets enter the capacitive state and store the value 0.
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At simulation time 50, the value of wire b changes to 1. This change of value in wire b connects trireg_sm to trireg_la; these trireg nets have different sizes and stored different values. This connection causes the smaller trireg net to store the value of the larger trireg net, and trireg_sm now stores a value of 0. This change of value in wire b also connects trireg_me1 to trireg_me2; these trireg nets have the same size and stored different values. The connection causes both trireg_me1 and trireg_me2 to change value to x.
Further Example: It shows the application of strength when trireg net enters in to the capacitive state.
This is the explanation of above CMOS circuit.
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The capacitive strength of trireg_la is large, and the capacitive strength of trireg_sm is small. Simulation reports the following results:
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At simulation time 0, the values of wire a, wire b, and wire c are 1, and wire a drive a strong 1 into trireg_la and trireg_sm.
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At simulation time 10, the value of wire b changes to 0, disconnecting trireg_la and trireg_sm from wire a. The trireg_la and trireg_sm nets enter the capacitive state. Both trireg nets share the large charge of trireg_la because they remain connected through tranif1_2.
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At simulation time 20, the value of wire c changes to 0, disconnecting trireg_sm from trireg_la. The trireg_sm no longer shares large charge of trireg_la and now stores a small charge.
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At simulation time 30, the value of wire c changes to 1, connecting the two trireg nets. These trireg nets now share the same charge.
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At simulation time 40, the value of wire c changes again to 0, disconnecting trireg_sm from trireg_la. Once again, trireg_sm no longer shares the large charge of trireg_la and now stores a small charge.