9.3 Module Port Mapping
Understanding Port Mapping
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Port mapping is the process of connecting signals between parent and child modules during instantiation. Proper port mapping is critical for correct design functionality and avoiding synthesis issues.
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Port Mapping Techniques
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9.3.1. Direct Mapping
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Simplest form where signal names match:
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9.3.2. Width Mismatch Handling
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When port widths don't match, proper handling is essential:
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9.3.3. Concatenation in Port Mapping
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Combining multiple signals:
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9.3.4. Bit Selection and Slicing
​Extracting specific bits:
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9.3.5. Unconnected Ports
Handling unused ports:
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9.3.6. Constant Connection
Connecting ports to fixed values:
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Advanced Port Mapping Examples
Bi-directional Port Mapping
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Interface-Based Mapping (SystemVerilog)
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Common Port Mapping Pitfalls
1. Width Mismatch Without Warning
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2. Floating Inputs
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3. Output Contention
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Port Mapping Best Practices
1. Always use named port connections for clarity
2. Handle width mismatches explicitly with concatenation or slicing
3. Tie off unused inputs to known values (0 or 1)
4. Document unusual mappings with comments
5. Check synthesis warnings for unconnected ports
6. Use parameters for configurable widths
7. Group related signals using SystemVerilog interfaces