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16.6.3. Repeat Loop
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The repeat loop executes a fixed number of times. Unlike for loops, it doesn't use a loop counter variable and is simpler when you just need N iterations. It is NOT synthesizable.
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Syntax and Structure
Verilog
Characteristics
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Executes exactly N times (N specified at loop creation)
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No loop counter variable needed
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Number of iterations evaluated ONCE at the start
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Simpler than for loop when counter not needed
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NOT synthesizable (testbench only)
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Basic Examples
Verilog
Repeat with Variable Count
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The iteration count is evaluated ONCE when the repeat statement is encountered.
Verilog
Common Repeat Loop Patterns
Verilog
Repeat vs For Loop
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