13.1 Continous Assignments

13.1. Continuous Assignment

The `assign` statement is the foundation of data flow modeling.

#Basic Syntax

assign <net> = <expression>;

Rules:

1. Left-hand side must be a net (wire), not a reg

2. Right-hand side can be any expression

3. Assignment is continuous (always active)

4. Multiple assignments allowed

5. Assignment executes whenever RHS changes

#Simple Examples

Verilog

Multiple Continuous Assignments

Verilog

Implicit Continuous Assignment

Can combine declaration and assignment:

Verilog

Continuous Assignment with Delays

Verilog

Note: Delays in continuous assignments are for simulation only and are typically ignored by synthesis tools.

Data flow modeling