14.4. Introduction to Timing Controls

Timing controls are fundamental mechanisms in Verilog that determine WHEN procedural statements execute. They provide the ability to model time delays, synchronize to events, and wait for specific conditions. Understanding timing controls is essential for writing effective testbenches and modeling realistic hardware behavior.

What are Timing Controls?

Timing controls suspend the execution of procedural statements until a specific time or condition is met. They are primarily used in:

Testbench stimulus generation

Clock and signal generation

Synchronization in behavioral models

Modeling propagation delays

RTL design (for synthesizable edge detection)

Types of Timing Controls

Synthesizability Note

CRITICAL:

Most timing controls are NOT synthesizable and should only be used in testbenches. The exception is event-based controls (@posedge, @negedge) which ARE synthesizable and form the basis of sequential logic design.

Below are the types and techniques through which timing of the digital circuit can be controlled:

14.4.1. Delay Based Timing Controls

14.4.2. Event Based Timing Controls

14.4.3. Level Sensitive Timing Controls

14.4.4. Advanced Timing Techniques