14.4.1. Delay-Based Timing Controls
Delay-based timing controls use the # symbol followed by a delay value to suspend execution for a specific amount of time. Delays are expressed in simulation time units.
14.4.1.1. Regular Delay Control (#delay)
Syntax and Basic Usage
Verilog
Characteristics
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Delays are CUMULATIVE in sequential blocks
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Execution suspends for the specified time
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NOT synthesizable (testbench use only)
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Can use expressions: #(period/2)
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Simulator advances time by delay amount
Delay Types
Verilog
Practical Examples
Verilog
14.4.1.2. Intra-Assignment Delay
Concept and Syntax
Intra-assignment delay places the delay AFTER the assignment operator. The RHS is evaluated immediately, but the assignment to LHS is delayed.
Verilog
Regular vs Intra-Assignment Delay
Verilog
Timing Diagram Comparison
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14.4.1.3. Zero Delay (#0)
Zero delay is a special case that doesn't advance simulation time but allows other scheduled events at the same time to execute first.
Purpose and Usage
Verilog
Used for:
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Avoiding race conditions
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Ensuring all concurrent events complete first
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Deterministic event ordering