14.2. Sequential and Parallel Blocks
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Within procedural blocks (initial or always), Verilog provides two mechanisms to control the execution flow of multiple statements: sequential blocks using begin-end and parallel blocks using fork-join.
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14.2.1. Sequential Blocks (begin-end)
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Characteristics
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Statements execute SEQUENTIALLY, one after another
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Delays are CUMULATIVE
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Each statement must complete before the next begins
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Most common in synthesis and testbenches
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Can be named for debugging purposes
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Syntax
Verilog
Timing in Sequential Blocks
Verilog
Timing Diagram:
.png)
Practical Examples
Example 1: Clock Generation
Verilog
Example 2: Test Stimulus Sequence
Verilog
14.2.2. Parallel Blocks (fork-join)
Characteristics
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Statements execute CONCURRENTLY (in parallel)
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Delays are RELATIVE to the start of the fork block
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All statements begin at the same time
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Block completes when ALL statements complete
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NOT synthesizable - testbench only
Syntax
Verilog
Timing in Parallel Blocks
Verilog
Timing Diagram:
.png)
Practical Examples
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Example: Multiple Concurrent Stimuli
Verilog
14.2.3. Comparison: Sequential vs Parallel
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Mixed Example
Verilog