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14.5.1. If/Else Statements
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The if/else statement is a conditional branching construct that evaluates boolean expressions and executes code based on whether the condition is true or false. Multiple conditions can be chained to create priority-encoded logic.
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Basic if Statement
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Syntax
Verilog
Example
Verilog
âš WARNING: This creates a LATCH because output_signal is not assigned when enable=0!
if/else Statement
Syntax
Verilog
Examples
Verilog
if/else-if/else Ladder
Syntax and Structure
The if-else-if ladder creates a PRIORITY structure where conditions are evaluated sequentially from top to bottom. The first TRUE condition executes, and remaining conditions are NOT evaluated.
Verilog
Priority Encoding Behavior
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X = Don't Care (not evaluated due to higher priority match)
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Practical Examples
Verilog
Nested if Statements
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if statements can be nested to create complex decision trees.
Verilog
Conditional Operators in if Statements
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