9.4 Design Module Fundamentals
Fundamental Design Principles
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Creating robust, synthesizable, and maintainable RTL code requires understanding key design principles. Let's explore the fundamentals that every VLSI engineer must master.
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Sequential vs. Combinational Logic
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Combinational Logic Design
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Combinational logic output depends only on current inputs:
Verilog
Key Rules for Combinational Logic:
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- Use `always @(*)` or `always_comb` (SystemVerilog)
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- All outputs must be assigned in all branches
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- Avoid latches by complete case statements
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- No clock or reset in sensitivity list
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Sequential Logic Design
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Sequential logic output depends on current inputs and previous state:
Verilog
Key Rules for Sequential Logic:
- Use edge-triggered always blocks (`posedge`/`negedge`)
- Use non-blocking assignments (`<=`)
- Include proper reset logic
- Separate sequential and combinational logic
Blocking vs. Non-Blocking Assignments
This is one of the most critical concepts in Verilog:
Verilog
Golden Rules:
1. Use non-blocking (<=) for sequential logic (always @(posedge clk))
2. Use blocking (=) for combinational logic (always @(*))
3. Don't mix blocking and non-blocking in the same always block
4. Use blocking for continuous assignments in testbenches
State Machine Design
State machines are fundamental to digital design. Here's a proper implementation:
Verilog
FSM Design Best Practices:
1. Separate state register, next-state logic, and output logic
2. Use meaningful state names with parameters
3. Include default cases to avoid latches
4. Consider one-hot vs. binary encoding
5. Document state transitions clearly
Reset Strategies
Asynchronous Reset (Most Common)
Verilog
Synchronous Reset
Verilog
Parameterization for Reusability
Verilog
Clock Domain Crossing (CDC)
When signals cross clock domains, special care is needed:
Verilog
Design Module Checklist
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Proper reset strategy (async/sync)
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Correct blocking/non-blocking usage
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Complete case statements (no latches)
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Parameterized for reusability
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Clock domain crossing handled
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Clear separation of sequential/combinational
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Meaningful signal names
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Comprehensive comments
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Synthesis guidelines followed