10.10. Verilog Concatenation Operator: Joining Bits and Buses
Introduction
The concatenation operator `{}` joins multiple operands—bits, vectors, or expressions—into a single vector. It's one of the most frequently used operators in Verilog, essential for building buses, extracting fields, packing/unpacking data, and creating complex bit patterns.
At VLSI Mentor, we emphasize that mastering concatenation is crucial for efficient data manipulation, protocol implementation, and clean RTL design.
10.10.1. Concatenation Operator Syntax
{operand1, operand2, operand3, ...}
Key Points:
- Joins operands left to right
- Creates a new vector
- Width = sum of all operand widths
- Can mix different types and widths
Basic Examples
Verilog
10.10.2. Building Buses
Creating Multi-Byte Buses
Verilog
Creating Address Buses
Verilog
10.10.3. Bit Field Extraction and Insertion
Extracting Bit Fields
Verilog
Inserting Bit Fields
Verilog
10.10.4. Packing and Unpacking Data
Data Packing
Verilog
Data Unpacking
Verilog
10.10.5. Practical Applications
Application 1: Carry and Sum from Addition
Verilog
Application 2: RGB Color Builder
Verilog
Application 3: Protocol Header Builder
Verilog
Application 4: Multi-Bit Mux Using Concatenation
Verilog
Application 5: Byte Swapping
Verilog
Application 6: Barrel Shifter Building Block
Verilog
10.10.6. Advanced Concatenation Techniques
Nested Concatenation
Verilog
Concatenation with Expressions
Verilog
Self-Referencing Concatenation
Verilog
Concatenation in Assignments
Left-Hand Side Concatenation
Verilog
Partial Assignments
Verilog
Common Use Cases
1. Build Word from Bytes
wire [31:0] word = {byte3, byte2, byte1, byte0};
2. Extract Carry and Sum
wire [8:0] temp = a + b;
assign {carry, sum} = temp;
3. Swap Bytes
wire [15:0] swapped = {data[7:0], data[15:8]};
4. Add Bits to Vector
wire [9:0] extended = {2'b00, data[7:0]};
5. Build Control Word
wire [7:0] control = {enable, rw, {6{1'b0}}};
10.10.7. Concatenation vs Replication
Verilog
10.10.8. Common Pitfalls
Pitfall 1: Width Mismatch
Verilog
Pitfall 2: Empty Concatenation
Verilog
Pitfall 3: Forgetting Bit Width
Verilog
10.10.9. Best Practices
✅ Use for building buses from smaller fields
✅ Use for extracting fields (LHS concatenation)
✅ Document field positions in comments
✅ Match total width to target
✅ Use replication for repeated patterns
❌ Don't create width mismatches
❌ Don't use empty concatenation
❌ Don't forget bit widths
10.10.10. Synthesis Behavior
Verilog
Width Calculation
Verilog