17.4. Path Delay Modeling
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Path delay modeling specifies delays from input pins to output pins, representing the actual signal propagation paths through hardware. This is the most accurate way to model timing.
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What is Path Delay?
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A path delay is the time it takes for a signal to propagate from an input port through the logic to an output port. Different paths may have different delays depending on:
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Logic depth
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Gate types in the path
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Load capacitance
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Wire delays
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Process variations
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Types of Paths
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17.4.1. Specify Blocks Overview
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Specify blocks are special constructs in Verilog designed specifically for timing specification. They separate timing information from functional description.
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Purpose of Specify Blocks
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Define path delays
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Specify timing checks
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Support SDF annotation
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Enable timing verification
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Maintain timing/logic separation
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Basic Structure
Verilog
17.4.2. Inside Specify Blocks
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Inside specify blocks, you can define various timing-related specifications using special syntax and system tasks.
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specparam - Timing Parameters
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specparam declares timing parameters that can be used throughout the specify block
Verilog
Path Delay Statements
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Parallel Connection (=>)
Verilog
Full Connection (*>)
Verilog
Edge-Sensitive Paths
Verilog
Conditional Paths
Verilog
Timing Check System Tasks
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Complete Example with All Elements
Verilog
Best Practices and Guidelines
Choosing the Right Delay Model
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Distributed: Behavioral/RTL simulation, quick prototyping
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Lumped: Simple modules, approximate timing
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Pin-to-Pin: Library cells, accurate timing, post-synthesis
General Guidelines
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Use specparam for named delays
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Include min:typ:max for flexibility
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Document delay units clearly
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Separate timing from functionality
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Add timing checks for sequential elements
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Use conditional paths for multiplexers