10.6. Verilog Relational Operators: Comparison and Decision Making
Introduction
Relational operators compare two operands and return a Boolean result (1-bit: true or false). They are fundamental for implementing comparators, threshold detectors, range checkers, and decision logic. Understanding how these operators work—especially the critical differences between signed and unsigned comparisons—is essential for writing correct RTL.
At VLSI Mentor, we emphasize that relational operators are not just for if-statements; they synthesize to real comparator hardware with area and timing implications.
10.6.1. Relational Operators Overview
⚠️ CRITICAL: The symbol `<=` has TWO different meanings:
1. Relational operator: Less than or equal (in expressions)
2. Non-blocking assignment: In always blocks
Context determines which one!
10.6.2. Truth Tables
Greater Than (>)
Less Than (<)
Greater or Equal (>=)
Less or Equal (<=)
10.6.3. Basic Examples
Verilog
10.6.4. Signed vs Unsigned Comparison
This is CRITICAL and causes many bugs!
Verilog
10.6.5. Context-Dependent <= Operator
Verilog
10.6.6. Practical Applications
Application 1: Range Checker
Verilog
Application 2: Multi-Level Threshold Detector
Verilog
Application 3: Magnitude Comparator
Verilog
Application 4: Min/Max Finder
Verilog
Application 5: FIFO Status Generator
Verilog
Application 6: Priority Encoder with Threshold
Verilog
10.6.7. Comparison with X and Z
Verilog
10.6.8. Hardware Implementation
Comparator Circuits
Verilog
10.6.9. Common Pitfalls
Pitfall 1: Mixing Signed/Unsigned
Verilog
Pitfall 2: Confusing <= Assignment and Comparison
Verilog
Pitfall 3: Not Considering Equal Case
Verilog
Best Practices
✅ Be explicit with types: Declare signed when needed
✅ Document thresholds: Use parameters
✅ Use meaningful names: `above_threshold` not `flag1`
✅ Consider edge cases: Equal values, min/max
✅ Comment comparisons: Explain threshold values
❌ Don't mix signed/unsigned: Cast explicitly
❌ Don't forget equal case: Handle `==` explicitly
10.6.10. Synthesis Considerations
Hardware Cost
Verilog
Critical Path
Verilog