10.8. Verilog Equality Operators: Testing for Equivalence
Introduction
Equality operators test whether two operands are equal or not equal. While this sounds simple, Verilog provides four different equality operators, each with distinct behavior regarding unknown (X) and high-impedance (Z) values. Understanding when to use each type is critical for writing correct RTL and testbenches.
At VLSI Mentor, we emphasize that choosing the right equality operator—especially the difference between logical and case equality—is essential for both synthesizable design and verification code.
10.8.1. Equality Operators Overview
10.8.2. Logical Equality (==)
Behavior
Returns 1 if operands are equal, 0 if different, X if any bit is X or Z.
Truth Table
Examples
Verilog
10.8.3. Logical Inequality (!=)
Behavior
Returns 1 if operands are different, 0 if equal, X if any bit is X or Z.
Examples
Verilog
10.8.4. Case Equality (===)
Behavior
Returns 1 if operands are exactly equal (including X and Z), 0 otherwise.
CRITICAL: This operator is NOT synthesizable - use only in testbenches!
Truth Table
Examples
Verilog
10.8.5. Case Inequality (!==)
Behavior
Returns 1 if operands are not exactly equal (including X and Z), 0 if exactly equal.
Examples
Verilog
10.8.6. == vs === Comparison
Side-by-Side Example
Verilog
10.8.7. Practical Applications
Application 1: State Machine (using ==)
Verilog
Application 2: Testbench Checking (using ===)
Verilog
Application 3: Self-Checking Testbench
Verilog
Application 4: Command Decoder
Verilog
Application 5: Data Comparator
Verilog
10.8.8. When to Use Each Operator
Use == and != for:
✅ Synthesizable RTL code
✅ State comparisons
✅ Data path logic
✅ Conditional statements
✅ Control logic
Verilog
✅ Testbench verification
✅ Checking for X or Z
✅ Exact value matching
✅ Simulation debugging
❌ NEVER in synthesizable code
Verilog
10.8.9. Common Pitfalls
Pitfall 1: Using === in Synthesizable Code
Verilog
Pitfall 2: Not Handling X in Testbenches
Verilog
Pitfall 3: Confusing Assignment with Equality
Verilog
10.8.10. Width Considerations
Verilog
10.8.11. Best Practices
✅ Use == and != in RTL (synthesizable)
✅ Use === and !== in testbenches (exact comparison)
✅ Check for specific values, not X/Z in RTL
✅ Use === to verify X/Z in testbenches
✅ Be aware of width differences
❌ Never use === in synthesizable code
❌ Don't confuse = (assign) with == (compare)
10.8.12. Synthesis Behavior
Verilog
10.8.13. Summary Table
