14.3. Blocking and Non-Blocking Assignments
​
Assignment statements are used to assign values to variables in procedural blocks. Verilog provides two types of assignments: blocking and non-blocking. Understanding the difference between these is CRITICAL for writing correct RTL code.
​
14.3.1. Blocking Assignments (=)
​
Characteristics
​
-
Uses the = operator
​
-
Executes IMMEDIATELY in sequential order
​
-
BLOCKS subsequent statements until complete
​
-
RHS evaluated and LHS updated immediately
​
-
Used for COMBINATIONAL logic
​
-
Order of statements matters!
​
Syntax and Behavior
Verilog
Execution Flow Example
Verilog
Result: a=1, b=1, c=1 (all updated in sequence)
Common Uses
Verilog
14.3.2. Non-Blocking Assignments (<=)
​
Characteristics
​
-
Uses the <= operator
​
-
Evaluates RHS immediately but schedules LHS update
​
-
Does NOT block subsequent statements
​
-
All updates happen at END of time step
​
-
Used for SEQUENTIAL logic (flip-flops)
​
-
Order of statements does NOT matter!
​
Syntax and Behavior
Verilog
Execution Flow Example
​
Assume: a=0, b=0, c=0 initially
Verilog
Result: Creates a shift register! Each uses old values.
​
Common Uses
Verilog
14.3.3. Critical Comparison
.png)
THE MOST IMPORTANT EXAMPLE
​
This example demonstrates WHY the choice of assignment type is critical:
​
Scenario: Creating a Shift Register
Verilog
14.3.4. Race Conditions and Determinism
​
Mixing blocking and non-blocking assignments in the same always block can lead to race conditions and non-deterministic behavior.
​
Race Condition Example
Verilog
The result is unpredictable because:
​
-
Different simulators may give different results
​
-
Synthesis vs simulation mismatch possible
​
-
Timing-dependent behavior
​
Multiple Driver Conflict
Verilog
Best Practices and Guidelines
​
1. Golden Rules for RTL Coding
​
-
Rule 1: Use non-blocking (<=) for sequential logic in always @(posedge clk)
​
-
Rule 2: Use blocking (=) for combinational logic in always @(*)
​
-
Rule 3: NEVER mix blocking and non-blocking in same always block
​
-
Rule 4: Assign each variable in only ONE always block
​
-
Rule 5: Use @(*) for combinational, not explicit lists
​
2. Coding Style Template
Verilog
3. Synthesis Considerations
.png)
Common Mistakes and How to Avoid Them
​
Mistake #1: Incomplete Sensitivity List
Verilog
Mistake #2: Unintentional Latches
Verilog
Mistake #3: Wrong Assignment Type
Verilog
Mistake #4: Mixing Assignment Types
Verilog
Mistake #5: Multiple Drivers
Verilog