14.3. Blocking and Non-Blocking Assignments
Assignment statements are used to assign values to variables in procedural blocks. Verilog provides two types of assignments: blocking and non-blocking. Understanding the difference between these is CRITICAL for writing correct RTL code.
14.3.1. Blocking Assignments (=)
Characteristics
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Uses the = operator
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Executes IMMEDIATELY in sequential order
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BLOCKS subsequent statements until complete
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RHS evaluated and LHS updated immediately
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Used for COMBINATIONAL logic
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Order of statements matters!
Syntax and Behavior
Verilog
Execution Flow Example
Verilog
Result: a=1, b=1, c=1 (all updated in sequence)
Common Uses
Verilog
14.3.2. Non-Blocking Assignments (<=)
Characteristics
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Uses the <= operator
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Evaluates RHS immediately but schedules LHS update
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Does NOT block subsequent statements
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All updates happen at END of time step
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Used for SEQUENTIAL logic (flip-flops)
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Order of statements does NOT matter!
Syntax and Behavior
Verilog
Execution Flow Example
Assume: a=0, b=0, c=0 initially
Verilog
Result: Creates a shift register! Each uses old values.
Common Uses
Verilog
14.3.3. Critical Comparison
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THE MOST IMPORTANT EXAMPLE
This example demonstrates WHY the choice of assignment type is critical:
Scenario: Creating a Shift Register
Verilog
14.3.4. Race Conditions and Determinism
Mixing blocking and non-blocking assignments in the same always block can lead to race conditions and non-deterministic behavior.
Race Condition Example
Verilog
The result is unpredictable because:
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Different simulators may give different results
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Synthesis vs simulation mismatch possible
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Timing-dependent behavior
Multiple Driver Conflict
Verilog
Best Practices and Guidelines
1. Golden Rules for RTL Coding
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Rule 1: Use non-blocking (<=) for sequential logic in always @(posedge clk)
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Rule 2: Use blocking (=) for combinational logic in always @(*)
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Rule 3: NEVER mix blocking and non-blocking in same always block
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Rule 4: Assign each variable in only ONE always block
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Rule 5: Use @(*) for combinational, not explicit lists
2. Coding Style Template
Verilog
3. Synthesis Considerations
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Common Mistakes and How to Avoid Them
Mistake #1: Incomplete Sensitivity List
Verilog
Mistake #2: Unintentional Latches
Verilog
Mistake #3: Wrong Assignment Type
Verilog
Mistake #4: Mixing Assignment Types
Verilog
Mistake #5: Multiple Drivers
Verilog