14.1. Behavioral Blocks (initial & always)
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Verilog provides two fundamental procedural blocks for behavioral modeling: the initial block and the always block. These blocks contain procedural statements that execute sequentially.
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14.1.1. The initial Block
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Syntax and Characteristics
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The initial block executes only once at the beginning of simulation at time t = 0.
Verilog
Key Properties
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Executes exactly ONCE at time t = 0
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Typically, NOT synthesizable (some exceptions for memory initialization)
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Primarily used in testbenches
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Can contain timing controls (#delay, @event, wait)
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Multiple initial blocks execute concurrently
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Common Applications
Verilog
14.1.2. The always Block
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Syntax and Characteristics
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The always block executes repeatedly throughout the simulation. It forms the core of RTL design and is synthesizable when written correctly.
Verilog
Sensitivity List
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The sensitivity list determines when the always block executes. It can contain:
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Edge-sensitive events: posedge clk, negedge reset
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Level-sensitive signals: @(a or b or c) or @(*)
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Mixed: @(posedge clk or negedge reset)
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Types of always Blocks
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A. Combinational Logic Always Block
Verilog
Key Points:
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Use blocking assignments (=)
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All inputs must be in sensitivity list or use @(*)
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All outputs must be assigned in all execution paths
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Synthesizes to combinational gates
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B. Sequential Logic Always Block
Verilog
Key Points:
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Use non-blocking assignments (<=)
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Sensitivity list contains only clock and reset edges
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Synthesizes to flip-flops/registers
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Asynchronous reset: negedge rst_n in sensitivity list
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Synchronous reset: no reset in sensitivity list
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C. Latched Logic (Unintended - Usually a Bug)
Verilog
2.3 Comparison: initial vs always
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