AMBA AHB — Tutorials · VLSI Mentor

179Total chapters

21Modules

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Built on the two-phase pipeline

Address/data overlap, HREADY wait states, and bursts taught as live transfer timing — not a flat signal list. You learn AHB the way it behaves on a bus.

Interview-ready depth

A dedicated interview module plus per-chapter interview weighting — wait states, arbitration, the AHB-to-APB bridge, and waveform reading.

Design → verify → debug

RTL templates (AHB-Lite slave, HREADYOUT, bridge FSM), SVA/UVM verification, and waveform-based debugging — the full engineering loop.

AMBA AHB Complete Curriculum

Your Learning Roadmap

179 chapters · 21 modules — the two-phase pipeline, wait states, bursts, and the bus matrix.

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Module 1

AHB Foundations

1.1Why AHB Exists 1.2The AMBA Family Overview 1.3AHB vs APB vs AXI 1.4Where AHB Is Used in SoCs 1.5The AHB Mental Model 1.6Shared Bus vs Interconnect Thinking 1.7Manager / Subordinate Terminology

Module 2

AHB Architecture

2.1AHB Bus Architecture 2.2Master, Slave, Decoder & Arbiter 2.3The Address / Control Phase 2.4The Data Phase 2.5Pipelined Operation 2.6Single Transfer vs Burst Transfer 2.7AHB-Lite Overview

Module 3

AHB Signal Deep Dive

3.1HCLK & HRESETn 3.2HADDR & HWRITE 3.3HTRANS 3.4HSIZE 3.5HBURST 3.6HPROT 3.7HWDATA & HRDATA 3.8HREADY & HREADYOUT 3.9HRESP 3.10HSEL 3.11HMASTER & HMASTLOCK 3.12HGRANT & HBUSREQ 3.13HSPLIT & HLOCK 3.14HNONSEC & HEXCL (Variants)

Module 4

Transfer Types (HTRANS)

4.1Transfer Types Overview 4.2IDLE Transfers 4.3BUSY Transfers 4.4NONSEQ Transfers 4.5SEQ Transfers 4.6How HTRANS Controls Bus Activity 4.7Valid Transfer Identification 4.8Common HTRANS Bugs

Module 5

Address and Data Phase

5.1The Two-Phase Pipeline 5.2Address Phase Leads Data Phase 5.3Control / Data Alignment 5.4Read Transfer Timing 5.5Write Transfer Timing 5.6Pipeline Hazards 5.7Phase Waveform Interpretation

Module 6

HREADY and Wait States

6.1What HREADY Means 6.2Slave-Inserted Wait States 6.3Master Behavior During Wait 6.4Holding Address & Control 6.5Data Phase Extension 6.6HREADY vs HREADYOUT 6.7Common Wait-State Bugs

Module 7

Responses

7.1OKAY Response 7.2ERROR Response 7.3RETRY Response 7.4SPLIT Response 7.5Response Timing 7.6The Two-Cycle ERROR Response 7.7How the Master Reacts 7.8AHB-Lite Response Simplification 7.9Debugging Bad Responses

Module 8

Burst Transfers

8.1Burst Overview 8.2SINGLE Transfers 8.3INCR (Undefined-Length) Bursts 8.4WRAP4 & INCR4 Bursts 8.5WRAP8 & INCR8 Bursts 8.6WRAP16 & INCR16 Bursts 8.7Burst Address Calculation 8.8Boundary Wrapping 8.9Beat Size 8.10Burst Termination 8.11BUSY Cycles Inside Bursts 8.12Common Burst Bugs

Module 9

Transfer Size and Alignment

9.1HSIZE Encoding 9.2Byte, Halfword & Word Transfers 9.3Aligned Access 9.4Unaligned Access Rules 9.5Lane Selection 9.6Endianness Considerations 9.7Write Strobes in Bridges 9.8Narrow Transfers

Module 10

Arbitration & Multi-Master AHB

10.1Why Arbitration Exists 10.2HBUSREQ & HGRANT 10.3HMASTER 10.4Locked Transfers (HLOCK)10.5Fixed-Priority Arbitration 10.6Round-Robin Arbitration 10.7Starvation 10.8Arbitration Timing 10.9Bus Ownership Handover

Module 11

Decoder & Slave Selection

11.1Address Decoding 11.2HSEL Generation 11.3The Default Slave 11.4The Address Map 11.5Illegal Address Behavior 11.6Sparse Memory Maps 11.7Peripheral Selection

Module 12

AHB-Lite

12.1Why AHB-Lite Exists 12.2Single-Master Simplification 12.3Removed Arbitration 12.4Simplified Responses 12.5Typical Microcontroller Use 12.6AHB-Lite Slave Design 12.7AHB-Lite vs Full AHB

Module 13

AHB Bus Matrix & Interconnect

13.1Multiple Masters 13.2Multiple Slaves 13.3The Bus Matrix Concept 13.4Parallel Slave Access 13.5Decoder + Arbiter Combination 13.6Interconnect Routing 13.7HREADY Aggregation 13.8Bus Matrix Performance

Module 14

Performance

14.1Throughput 14.2Latency 14.3Pipelining Benefit 14.4Wait-State Penalty 14.5Burst Efficiency 14.6Arbitration Overhead 14.7Bridge Penalty 14.8Memory / Peripheral Bottlenecks 14.9Performance Debug

Module 15

Reset and Clocking

15.1HRESETn Behavior 15.2Reset-Safe Transfers 15.3Reset During an Active Transfer 15.4Clock Gating Considerations 15.5Low-Power Implications 15.6CDC Bridges

Module 16

AHB RTL Design

16.1A Simple AHB-Lite Slave 16.2Register Bank Slave 16.3Memory Slave 16.4HREADYOUT Generation 16.5HRDATA Muxing 16.6HRESP Generation 16.7Address / Control Capture 16.8Write FSM 16.9Read FSM 16.10Bridge FSM (RTL)16.11Reusable AHB RTL Templates

Module 17

AHB Verification

17.1The Protocol-Checker Mindset 17.2AHB Assertions (SVA)17.3AHB Monitors 17.4AHB Scoreboards 17.5AHB Functional Coverage 17.6Constrained-Random AHB Traffic 17.7Wait-State Testing 17.8Burst Testing 17.9Error-Response Testing 17.10Bridge Verification 17.11UVM AHB Agent Overview

Module 18

AHB Debugging

18.1Stuck HREADY 18.2Wrong HTRANS 18.3Address / Data Misalignment 18.4Incorrect HSEL 18.5Wrong HRDATA Timing 18.6Bad HRESP 18.7Burst Wrap Error 18.8Arbitration Bug 18.9Bridge Deadlock 18.10Waveform-Based Debug Methodology

Module 19

Interview Mastery

19.1Beginner Interview Questions 19.2Intermediate Interview Questions 19.3Advanced Interview Questions 19.4Waveform Interpretation Questions 19.5Design Interview Questions 19.6Verification Interview Questions 19.7Bridge Interview Questions 19.8Arbitration Interview Questions 19.9Tricky Misconceptions

Module 20

Industry Case Studies

20.1CPU to SRAM 20.2CPU to Peripheral via AHB/APB Bridge 20.3DMA Master on AHB 20.4Boot ROM Access 20.5Debug Subsystem 20.6Microcontroller Bus Fabric 20.7Low-Power Peripheral Access

Module 21

Final AHB Checklist

21.1AHB Design Checklist 21.2AHB Verification Checklist 21.3AHB Integration Checklist 21.4AHB Waveform Checklist 21.5AHB Interview Checklist 21.6Common Mistakes Checklist